EDD5108AFTA, EDD5116AFTA
AC Characteristics (TA = 0°C to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V) [DDR333, 266]
-6B
Parameter
Clock cycle time
(CL = 2)
(CL = 2.5)
CK high-level width
CK low-level width
CK half period
Symbol
tCK
tCK
tCH
tCL
tHP
min.
7.5
6
0.45
0.45
min
(tCH, tCL)
–0.7
max.
12
12
0.55
0.55
—
0.7
0.6
0.45
-7A
min.
7.5
7.5
0.45
0.45
min
(tCH, tCL)
–0.75
–0.75
—
max
12
12
0.55
0.55
—
0.75
0.75
0.5
-7B
min.
10
7.5
0.45
0.45
min
(tCH, tCL)
–0.75
–0.75
—
max.
12
12
0.55
0.55
—
0.75
0.75
0.5
Unit Notes
ns
ns
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
ns
ns
ns
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ns
ns
ns
tCK
ns
ns
ns
ns
ns
ns
ns
8
8
7
9
8
8
7
5, 11
6, 11
2, 11
2, 11
3
10
DQ output access time from CK, /CK tAC
DQS output access time from CK,
/CK
DQS to DQ skew
tDQSCK –0.6
tDQSQ
—
DQ/DQS output hold time from DQS tQH
Data hold skew factor
Data-out high-impedance time from
CK, /CK
Data-out low-impedance time from
CK, /CK
Read preamble
Read postamble
DQ and DM input setup time
DQ and DM input hold time
DQ and DM input pulse width
Write preamble setup time
Write preamble
Write postamble
tQHS
tHZ
tLZ
tRPRE
tRPST
tDS
tDH
tDIPW
tHP – tQHS —
—
—
–0.7
0.9
0.4
0.45
0.45
1.75
0.55
0.7
0.7
1.1
0.6
—
—
—
—
—
0.6
1.25
—
—
—
tHP – tQHS —
—
—
–0.75
0.9
0.4
0.5
0.5
1.75
0
0.25
0.4
0.75
0.2
0.2
0.35
0.35
0.75
0.75
0.75
1.1
0.6
—
—
—
—
—
0.6
1.25
—
—
—
—
—
—
—
—
120000
—
—
—
—
—
—
tHP – tQHS —
—
—
–0.75
0.9
0.4
0.5
0.5
1.75
0
0.25
0.4
0.75
0.2
0.2
0.35
0.35
0.9
0.9
2.2
2
45
65
75
20
20
tRCD min.
15
0.75
0.75
0.75
1.1
0.6
—
—
—
—
—
0.6
1.25
—
—
—
—
—
—
—
—
120000
—
—
—
—
—
—
tWPRES 0
tWPRE
tWPST
0.25
0.4
0.75
0.2
0.2
0.35
0.35
0.75
0.75
2.2
2
42
60
72
18
18
tRCD min.
12
Write command to first DQS latching
tDQSS
transition
DQS falling edge to CK setup time
DQS falling edge hold time from CK
DQS input high pulse width
DQS input low pulse width
tDSS
tDSH
tDQSH
tDQSL
Address and control input setup time tIS
Address and control input hold time
Mode register set command cycle
time
Active to Active/Auto-refresh
command period
Auto-refresh to Active/Auto-refresh
command period
Active to Read/Write delay
tIH
—
—
—
—
120000
—
—
—
—
—
—
0.9
0.9
2.2
2
45
65
75
20
20
tRCD min.
15
Address and control input pulse width tIPW
tMRD
Active to Precharge command period tRAS
tRC
tRFC
tRCD
Precharge to active command period tRP
Active to Autoprecharge delay
Active to active command period
tRAP
tRRD
Data Sheet E0699E50 (Ver. 5.0)
9
ELPIDA [ ELPIDA MEMORY ]
