EDD5108AGTA, EDD5116AGTA
Notes: 1. These IDD data are measured under condition that DQ pins are not connected.
2. One bank operation.
3. One bank active.
4. All banks idle.
5. Command/Address transition once per one clock cycle.
6. DQ, DM and DQS transition twice per one clock cycle.
7. 4 banks active. Only one bank is running at tRC = tRC (min.)
8. The IDD data on this table are measured with regard to tCK = tCK (min.) in general.
9. Command/Address transition once every two clock cycle.
10. Command/Address stable at
≥
VIH or
≤
VIL.
DC Characteristics 2 (TA = 0°C to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V)
Parameter
Input leakage current
Output leakage current
Output high current
Output low current
Symbol
ILI
ILO
IOH
IOL
min.
–2
–5
–15.2
15.2
max.
2
5
—
—
Unit
µA
µA
mA
mA
Test condition
VDD
≥
VIN
≥
VSS
VDDQ
≥
VOUT
≥
VSS
VOUT = 1.95V
VOUT = 0.35V
Notes
Pin Capacitance (TA = +25°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V)
Parameter
Input capacitance
Symbol
CI1
CI2
Delta input capacitance
Cdi1
Cdi2
Data input/output capacitance
Delta input/output capacitance
CI/O
Cdio
Pins
CK, /CK
All other input pins
CK, /CK
All other input-only pins
DQ, DM, DQS
DQ, DM, DQS
min.
2.0
2.0
—
—
4.0
—
typ.
—
—
—
—
—
—
max.
3.0
3.0
0.25
0.5
5
0.5
Unit
pF
pF
pF
pF
pF
pF
Notes
1
1
1
1
1, 2
1
Notes: 1. These parameters are measured on conditions: f = 100MHz, VOUT = VDDQ/2,
ΔVOUT
= 0.2V.
2. DOUT circuits are disabled.
Data Sheet E1191E20 (Ver. 2.0)
7
ELPIDA [ ELPIDA MEMORY ]
