欢迎访问ic37.com |
会员登录 免费注册
发布采购

EDD5108ADTA-6B 参数 Datasheet PDF下载

EDD5108ADTA-6B图片预览
型号: EDD5108ADTA-6B
PDF下载: 下载PDF文件 查看货源
内容描述: 512M比特DDR SDRAM [512M bits DDR SDRAM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 49 页 / 462 K
品牌: ELPIDA [ ELPIDA MEMORY ]
 浏览型号EDD5108ADTA-6B的Datasheet PDF文件第1页浏览型号EDD5108ADTA-6B的Datasheet PDF文件第2页浏览型号EDD5108ADTA-6B的Datasheet PDF文件第3页浏览型号EDD5108ADTA-6B的Datasheet PDF文件第4页浏览型号EDD5108ADTA-6B的Datasheet PDF文件第6页浏览型号EDD5108ADTA-6B的Datasheet PDF文件第7页浏览型号EDD5108ADTA-6B的Datasheet PDF文件第8页浏览型号EDD5108ADTA-6B的Datasheet PDF文件第9页  
EDD5104ADTA, EDD5108ADTA, EDD5116ADTA
DC Characteristics 1 (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V)
°
max.
Parameter
Operating current (ACT-
PRE)
Operating current
(ACT-READ-PRE)
Symbol
IDD0
IDD1
Grade
-6B
-7A, -7B
-6B
-7A, -7B
×
4
150
135
190
170
3
-6B
-7A, -7B
30
25
20
20
-6B
-7A, -7B
-6B
-7A, -7B
-6B
-7A, -7B
-6B
-7A, -7B
65
55
230
200
230
200
320
300
4
-xxL
-6B
-7A, -7B
3
490
410
×
8
150
135
200
175
3
30
25
20
20
65
55
250
210
250
210
320
300
4
3
510
430
×
16
150
135
210
180
3
30
25
20
20
65
55
270
230
270
230
320
300
4
3
530
450
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
BL = 4
1, 5, 6, 7
Test condition
CKE
VIH,
tRC = tRC (min.)
CKE
VIH, BL = 4,
CL = 2.5,
tRC = tRC (min.)
CKE
VIL
CKE
VIH, /CS
VIH,
DQ, DQS, DM = VREF
CKE
VIH, /CS
VIH,
DQ, DQS, DM = VREF
CKE
VIL
CKE
VIH, /CS
VIH
tRAS = tRAS (max.)
CKE
VIH, BL = 2,
CL = 2.5
CKE
VIH, BL = 2,
CL = 2.5
tRFC = tRFC (min.),
Input
VIL or
VIH
Input
VDD – 0.2 V
Input
0.2 V
Notes
1, 2, 9
1, 2, 5
4
4, 5
4, 10
3
3, 5, 6
1, 2, 5, 6
1, 2, 5, 6
Idle power down standby
IDD2P
current
Floating idle standby
IDD2F
current
Quiet idle standby current IDD2Q
Active power down
standby current
Active standby current
Operating current
(Burst read operation)
Operating current
(Burst write operation)
Auto Refresh current
Self refresh current
Self refresh current
((L-version))
Operating current
(4 banks interleaving)
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD6
IDD7A
Notes: 1. These IDD data are measured under condition that DQ pins are not connected.
2. One bank operation.
3. One bank active.
4. All banks idle.
5. Command/Address transition once per one clock cycle.
6. DQ, DM and DQS transition twice per one clock cycle.
7. 4 banks active. Only one bank is running at tRC = tRC (min.)
8. The IDD data on this table are measured with regard to tCK = tCK (min.) in general.
9. Command/Address transition once every two clock cycles.
10. Command/Address stable at
VIH or
VIL.
DC Characteristics 2 (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V)
°
Parameter
Input leakage current
Output leakage current
Output high current
Output low current
Symbol
ILI
ILO
IOH
IOL
min.
–2
–5
–15.2
15.2
max.
2
5
Unit
µA
µA
mA
mA
Test condition
VDD
VIN
VSS
VDDQ
VOUT
VSS
VOUT = 1.95V
VOUT = 0.35V
Notes
Data Sheet E0384E30 (Ver. 3.0)
5