PRELIMINARY DATA SHEET
512M bits DDR SDRAM
EDD5104ABTA (128M words
×
4 bits)
EDD5108ABTA (64M words
×
8 bits)
Description
The EDD5104AB is a 512M bits Double Data Rate
(DDR) SDRAM organized as 33,554,432 words
×
4 bits
×
4 banks. The EDD5108AB is a 512M bits DDR
SDRAM organized as 16,777,216 words
×
8 bits
×
4
banks. Read and write operations are performed at the
cross points of the CK and the /CK. This high-speed
data transfer is realized by the 2 bits prefetch-pipelined
architecture. Data strobe (DQS) both for read and
write are available for high speed and reliable data bus
design. By setting extended mode resistor, the on-chip
Delay Locked Loop (DLL) can be set enable or disable.
They are packaged in standard 66-pin plastic TSOP
(II)10.16mm(400).
Pin Configurations
/xxx indicates active low signal.
66-pin TSOP(II)10.16mm(400)
VDD
VDD
NC
DQ0
VDDQ VDDQ
NC
NC
DQ0
DQ1
VSSQ VSSQ
NC
NC
NC
DQ2
VDDQ VDDQ
NC
NC
DQ1
DQ3
VSSQ VSSQ
NC
NC
NC
NC
VDDQ VDDQ
NC
NC
NC
NC
VDD
VDD
NC
NC
NC
NC
/WE
/WE
/CAS
/CAS
/RAS
/RAS
/CS
/CS
NC
NC
BA0
BA0
BA1
BA1
A10(AP) A10(AP)
A0
A0
A1
A1
A2
A2
A3
A3
VDD
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
/CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
VSS
NC
VSSQ
NC
DQ3
VDDQ
NC
NC
VSSQ
NC
DQ2
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
/CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
Features
•
2.5 V power supply: VDDQ = 2.5V
±
0.2V
: VDD = 2.5V
±
0.2V
•
Data Rate: 333Mbps/266Mbps (max.)
•
Double Data Rate architecture; two data transfers per
clock cycle
•
Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
•
Data inputs, outputs, and DM are synchronized with
DQS
•
4 internal banks for concurrent operation
•
DQS is edge aligned with data for READs; center
aligned with data for WRITEs
•
Differential clock inputs (CK and /CK)
•
DLL aligns DQ and DQS transitions with CK
transitions
•
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
•
Data mask (DM) for write data
•
Auto precharge option for each burst access
•
2.5 V (SSTL_2 compatible) I/O
•
Programmable burst length (BL): 2, 4, 8
•
Programmable /CAS latency (CL): 2, 2.5
•
Refresh cycles: 8192 refresh cycles/64ms
7.8µs maximum average periodic refresh interval
•
2 variations of refresh
Auto refresh
Self refresh
Document No. E0237E30 (Ver. 3.0)
Date Published August 2002 (K) Japan
URL: http://www.elpida.com
X8
X4
(Top view)
A0 to A12
BA0, BA1
DQ0 to DQ7
DQS
/CS
/RAS
/CAS
/WE
DM
CK
/CK
CKE
VREF
VDD
VSS
VDDQ
VSSQ
NC
Address input
Bank select address
Data-input/output
Input and output data strobe
Chip select
Row address strobe command
Column address strobe command
Write enable
Input mask
Clock input
Differential clock input
Clock enable
Input reference voltage
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Elpida
Memory, Inc. 2002
ELPIDA [ ELPIDA MEMORY ]
