DATA SHEET
1G bits DDR2 SDRAM
WTR (Wide Temperature Range)
EDE1116ACSE-LI (64M words
×
16 bits)
Specifications
•
Density: 1G bits
•
Organization
8M words
×
16 bits
×
8 banks
•
Package
84-ball FBGA
Lead-free (RoHS compliant)
•
Power supply: VDD, VDDQ
=
1.8V
±
0.1V
•
Data rate: 667Mbps (max.)
•
2KB page size
Row address: A0 to A12
Column address: A0 to A9
•
Eight internal banks for concurrent operation
•
Interface: SSTL_18
•
Burst lengths (BL): 4, 8
•
Burst type (BT):
Sequential (4, 8)
Interleave (4, 8)
•
/CAS Latency (CL): 3, 4, 5
•
Precharge: auto precharge option for each burst
access
•
Driver strength: normal/weak
•
Refresh: auto-refresh, self-refresh
Features
•
Double-data-rate architecture; two data transfers per
clock cycle
•
The high-speed data transfer is realized by the 4 bits
prefetch pipelined architecture
•
Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
•
DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
•
Differential clock inputs (CK and /CK)
•
DLL aligns DQ and DQS transitions with CK
transitions
•
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
•
Data mask (DM) for write data
•
Posted /CAS by programmable additive latency for
better command and data bus efficiency
•
Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
•
/DQS can be disabled for single-ended Data Strobe
operation
•
Wide temperature range
TC =
−40°C
to +95°C
•
Refresh cycles: 8192 cycles/64ms
Average refresh period: 7.8µs
•
Operating case temperature range
TC =
−40°C
to +95°C
Document No. E1103E20 (Ver. 2.0)
Date Published June 2008 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida
Memory, Inc. 2007-2008
ELPIDA [ ELPIDA MEMORY ]
