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EDE2116AEBG-8E-F 参数 Datasheet PDF下载

EDE2116AEBG-8E-F图片预览
型号: EDE2116AEBG-8E-F
PDF下载: 下载PDF文件 查看货源
内容描述: 2G位DDR2 SDRAM [2G bits DDR2 SDRAM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 73 页 / 515 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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EDE2116AEBG  
DC Characteristics 1 (TC = 0°C to +85°C, VDD, VDDQ = 1.8V ± 0.1V)  
Parameter  
Symbol Grade  
max.  
Unit Test condition  
one bank; tCK = tCK (IDD), tRC = tRC (IDD),  
tRAS = tRAS min.(IDD);  
Operating current  
(ACT-PRE)  
IDD0  
60  
mA  
CKE is H, /CS is H between valid commands;  
Address bus inputs are SWITCHING;  
Data bus inputs are SWITCHING  
one bank; IOUT = 0mA;  
BL = 4, CL = CL(IDD), AL = 0;  
tCK = tCK (IDD), tRC = tRC (IDD),  
tRAS = tRAS min.(IDD); tRCD = tRCD (IDD);  
CKE is H, /CS is H between valid commands;  
Address bus inputs are SWITCHING;  
Data pattern is same as IDD4W  
Operating current  
(ACT-READ-PRE)  
IDD1  
75  
mA  
all banks idle;  
tCK = tCK (IDD);  
CKE is L;  
Other control and address bus inputs are STABLE;  
Data bus inputs are FLOATING  
Precharge power-down  
standby current  
IDD2P  
IDD2Q  
IDD2N  
12  
20  
25  
mA  
mA  
mA  
all banks idle;  
tCK = tCK (IDD);  
CKE is H, /CS is H;  
Other control and address bus inputs are STABLE;  
Data bus inputs are FLOATING  
Precharge quiet standby  
current  
all banks idle;  
tCK = tCK (IDD);  
CKE is H, /CS is H;  
Idle standby current  
Other control and address bus inputs are SWITCHING;  
Data bus inputs are SWITCHING  
all banks open;  
tCK = tCK (IDD);  
CKE is L;  
Fast PDN Exit  
MRS (12) = 0  
IDD3P-F  
IDD3P-S  
25  
14  
mA  
mA  
Active power-down  
standby current  
Other control and address  
bus inputs are STABLE;  
Data bus inputs are  
MRS (12) = 1  
FLOATING  
Slow PDN Exit  
all banks open;  
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);  
CKE is H, /CS is H between valid commands;  
Other control and address bus inputs are SWITCHING;  
Data bus inputs are SWITCHING  
Active standby current  
IDD3N  
IDD4R  
45  
mA  
mA  
all banks open, continuous burst reads, IOUT = 0mA;  
BL = 4, CL = CL(IDD), AL = 0;  
tCK = tCK (IDD), tRAS = tRAS max.(IDD),  
tRP = tRP (IDD);  
CKE is H, /CS is H between valid commands;  
Address bus inputs are SWITCHING;  
Data pattern is same as IDD4W  
Operating current  
(Burst read operating)  
120  
all banks open, continuous burst writes;  
BL = 4, CL = CL(IDD), AL = 0;  
tCK = tCK (IDD), tRAS = tRAS max.(IDD),  
tRP = tRP (IDD);  
CKE is H, /CS is H between valid commands;  
Address bus inputs are SWITCHING;  
Data bus inputs are SWITCHING  
Operating current  
(Burst write operating)  
IDD4W  
IDD5  
140  
150  
mA  
mA  
tCK = tCK (IDD);  
Refresh command at every tRFC (IDD) interval;  
CKE is H, /CS is H between valid commands;  
Other control and address bus inputs are SWITCHING;  
Data bus inputs are SWITCHING  
Auto-refresh current  
Data Sheet E1820E21 (Ver.2.1)  
8