PRELIMINARY DATA SHEET
256M bits DDR2 SDRAM
EDE2504AASE (64M words
×
4 bits)
EDE2508AASE (32M words
×
8 bits)
EDE2516AASE (16M words
×
16 bits)
Description
The EDE2504AA is a 256M bits DDR2 SDRAM
organized as 16,777,216 words
×
4 bits
×
4 banks.
The EDE2508AA is a 256M bits DDR2 SDRAM
organized as 8,388,608 words
×
8 bits
×
4 banks.
They are packaged in 64-ball FBGA package.
The EDE2516AA is a 256M bits DDR2 SDRAM
organized as 4,194,304 words
×
16 bits
×
4 banks.
It is packaged in 84-ball FBGA package.
Features
•
1.8V power supply
•
Double-data-rate architecture: two data transfers per
clock cycle
•
Bi-directional, differential data strobe (DQS and
/DQS) is transmitted/received with data, to be used in
capturing data at the receiver
•
DQS is edge aligned with data for READs: center-
aligned with data for WRITEs
•
Differential clock inputs (CK and /CK)
•
DLL aligns DQ and DQS transitions with CK
transitions
•
Commands entered on each positive CK edge: data
and data mask referenced to both edges of DQS
•
Four internal banks for concurrent operation
•
Data mask (DM) for write data
•
Burst lengths: 4, 8
•
/CAS Latency (CL): 3, 4, 5
•
Auto precharge operation for each burst access
•
Auto refresh and self refresh modes
•
7.8µs average periodic refresh interval
•
1.8V (SSTL_18 compatible) I/O
•
Posted CAS by programmable additive latency for
better command and data bus efficiency
•
Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
•
Programmable RDQS, /RDQS output for making
×
8
organization compatible to
×
4 organization
•
/DQS, (/RDQS) can be disabled for single-ended
Data Strobe operation.
•
FBGA package is lead free solder (Sn-Ag-Cu)
Document No. E0427E11 (Ver. 1.1)
Date Published February 2006 (K) Japan
URL: http://www.elpida.com
Elpida
Memory, Inc. 2003-2006
ELPIDA [ ELPIDA MEMORY ]
