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EDE2508AASE-BE-E 参数 Datasheet PDF下载

EDE2508AASE-BE-E图片预览
型号: EDE2508AASE-BE-E
PDF下载: 下载PDF文件 查看货源
内容描述: 256M位DDR2 SDRAM用于Hyper DIMM [256M bits DDR2 SDRAM for HYPER DIMM]
分类和应用: 存储内存集成电路动态存储器双倍数据速率
文件页数/大小: 66 页 / 673 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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PRELIMINARY DATA SHEET
256M bits DDR2 SDRAM
for HYPER DIMM
EDE2508AASE-DF, -BE, -AE (32M words
×
8 bits)
EDE2516AASE-DF, -BE, -AE (16M words
×
16 bits)
Description
The EDE2508AA is a 256M bits DDR2 SDRAM
organized as 8,388,608 words
×
8 bits
×
4 banks.
It is packaged in 64-ball FBGA package.
The EDE2516AA is a 256M bits DDR2 SDRAM
organized as 4,194,304 words
×
16 bits
×
4 banks.
It is packaged in 84-ball FBGA package.
Features
1.8V power supply
Double-data-rate architecture: two data transfers per
clock cycle
Bi-directional, differential data strobe (DQS and
/DQS) is transmitted/received with data, to be used in
capturing data at the receiver
DQS is edge aligned with data for READs: center-
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge: data
and data mask referenced to both edges of DQS
Four internal banks for concurrent operation
Data mask (DM) for write data
Burst lengths: 4, 8
/CAS Latency (CL): 3, 4, 5
Auto precharge operation for each burst access
Auto refresh and self refresh modes
7.8µs average periodic refresh interval
1.8V (SSTL_18 compatible) I/O
Posted CAS by programmable additive latency for
better command and data bus efficiency
Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
Programmable RDQS, /RDQS output for making
×
8
organization compatible to
×
4 organization
/DQS, (/RDQS) can be disabled for single-ended
Data Strobe operation.
FBGA package with lead free solder (Sn-Ag-Cu)
Document No. E0515E12 (Ver. 1.2)
Date Published February 2006 (K) Japan
URL: http://www.elpida.com
Elpida
Memory, Inc. 2004-2006