EDE2508AASE/16AASE-DF, -BE, -AE
max.
Parameter
Symbol
Grade
-DF
Auto-refresh current
IDD5
-BE
-AE
×
8
270
270
260
×
16
270
270
260
mA
Unit
Test condition
tCK = tCK (IDD);
Refresh command at every tRFC (IDD) interval;
CKE is H, /CS is H between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Self Refresh Mode;
CK and /CK at 0V;
CKE
≤
0.2V;
Other control and address bus inputs are FLOATING;
Data bus inputs are FLOATING
all bank interleaving reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = tRCD (IDD)
−1
×
tCK (IDD);
tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD(IDD),
tRCD = 1
×
tCK (IDD); See Notes 7;
CKE is H, CS is H between valid commands;
Address bus inputs are STABLE during DESELECTs;
Data pattern is same as IDD4W;
Self-refresh current
IDD6
6
6
mA
-DF
Operating current
(Bank interleaving)
IDD7
-BE
-AE
340
340
330
475
475
460
mA
Notes: 1.
2.
3.
4.
IDD specifications are tested after the device is properly initialized.
Input slew rate is specified by AC Input Test Condition.
IDD parameters are specified with ODT disabled.
Data bus consists of DQ, DM, DQS, /DQS, RDQS, /RDQS, LDQS, /LDQS, UDQS, and /UDQS. IDD
values must be met with all combinations of EMRS bits 10 and 11.
5. Definitions for IDD
L is defined as VIN
≤
VIL (AC) (max.)
H is defined as VIN
≥
VIH (AC) (min.)
STABLE is defined as inputs stable at an H or L level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as:
inputs changing between H and L every other clock cycle (once per two clocks) for address and control
signals, and inputs changing between H and L every other data transfer (once per clock) for DQ signals
not including masks or strobes.
6. Refer to AC Timing for IDD Test Conditions.
7. In case of -DF (DDR2-700), tRCD must be 2
×
tCK (IDD) and AL must be 4
×
tCK (IDD) because AL = 5 is
not supported in this device.
AC Timing for IDD Test Conditions
For purposes of IDD testing, the following parameters are to be utilized.
DDR2-700
Parameter
CL(IDD)
tRCD(IDD)
tRC(IDD)
tRRD(IDD)
tCK(IDD)
tRAS(min.)(IDD)
tRAS(max.)(IDD)
tRP(IDD)
tRFC(IDD)
5-6-6
5
15
67.5
7.5
2.85
50
70000
15
85
DDR2-667
5-5-5
5
15
60
7.5
3
45
70000
15
75
DDR2-600
5-5-5
5
15
65
7.5
3.3
47.5
70000
15
80
Unit
tCK
ns
ns
ns
ns
ns
ns
ns
ns
Preliminary Data Sheet E0515E12 (Ver. 1.2)
8
ELPIDA [ ELPIDA MEMORY ]
