EDE5104AGSE, EDE5108AGSE
AC Characteristics (TC = 0°C to +85°C, VDD, VDDQ = 1.8V
±
0.1V, VSS, VSSQ = 0V)
-6C, -6E
Frequency (Mbps)
Parameter
/CAS latency
Active to read or write command
delay
Precharge command period
Active to active/auto refresh
command time
DQS output access time from CK,
/CK
CK high-level width
CK low-level width
CK half period
Clock cycle time
DQ and DM input hold time
DQ and DM input setup time
Control and Address input pulse
width for each input
DQ and DM input pulse width for
each input
Data-out high-impedance time from
CK,/CK
Data-out low-impedance time from
CK,/CK
DQS-DQ skew for DQS and
associated DQ signals
DQ hold skew factor
Symbol
CL
tRCD
tRP
tRC
667
min.
4 (-6C)
5 (-6E)
12 (-6C)
15 (-6E)
12 (-6C)
15(-6E)
57 (-6C)
60 (-6E)
−450
max.
5
+450
+400
0.55
0.55
-5C
533
min.
4
15
15
60
−500
−450
0.45
0.45
max.
5
+500
+450
0.55
0.55
-4A
400
min.
3
15
15
55
−600
−500
0.45
0.45
max.
5
+600
+500
0.55
0.55
Unit
tCK
ns
ns
ns
ps
ps
tCK
tCK
ps
ps
ps
ps
tCK
tCK
ps
ps
ps
ps
ps
5
4
Notes
DQ output access time from CK, /CK tAC
tDQSCK
−400
tCH
tCL
tHP
tCK
tDH
tDS
tIPW
tDIPW
tHZ
tLZ
tDQSQ
tQHS
0.45
0.45
min.
(tCL, tCH)
3000
175
100
0.6
0.35
tAC min.
tHP –
tQHS
8000
tAC max.
tAC max.
240
340
min.
(tCL, tCH)
3750
225
100
0.6
0.35
tAC min.
tHP –
tQHS
8000
tAC max.
tAC max.
300
400
min.
(tCL, tCH)
5000
275
150
0.6
0.35
tAC min.
tHP –
tQHS
8000
tAC max.
tAC max.
350
450
DQ/DQS output hold time from DQS tQH
Write command to first DQS latching
tDQSS
transition
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK setup time
tDQSH
tDQSL
tDSS
WL
−
0.25 WL + 0.25 WL
−
0.25 WL + 0.25 WL
−
0.25 WL + 0.25 tCK
0.35
0.35
0.2
0.2
2
0.4
0.35
275
200
0.9
0.4
45
0.6
1.1
0.6
70000
0.35
0.35
0.2
0.2
2
0.4
0.35
375
250
0.9
0.4
45
0.6
1.1
0.6
70000
0.35
0.35
0.2
0.2
2
0.4
0.35
475
350
0.9
0.4
40
0.6
1.1
0.6
70000
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ps
ps
tCK
tCK
ns
ns
5
4
DQS falling edge hold time from CK tDSH
Mode register set command cycle
time
Write postamble
Write preamble
Address and control input hold time
tMRD
tWPST
tWPRE
tIH
Address and control input setup time tIS
Read preamble
Read postamble
Active to precharge command
Active to auto-precharge delay
tRPRE
tRPST
tRAS
tRAP
tRCD min.
tRCD min.
tRCD min.
Preliminary Data Sheet E0715E20 (Ver. 2.0)
12
ELPIDA [ ELPIDA MEMORY ]
