DATA SHEET
512M bits DDR2 SDRAM
EDE5116AFSE (32M words
×
16 bits)
Description
The EDE5116AFSE is a 512M bits DDR2 SDRAM
organized as 8,388,608 words
×
16 bits
×
4 banks.
It is packaged in 84-ball FBGA (µBGA
) package.
Features
•
Power supply: VDD, VDDQ
=
1.8V
±
0.1V
•
Double-data-rate architecture: two data transfers per
clock cycle
•
Bi-directional, differential data strobe (DQS and
/DQS) is transmitted/received with data, to be used in
capturing data at the receiver
•
DQS is edge aligned with data for READs: center-
aligned with data for WRITEs
•
Differential clock inputs (CK and /CK)
•
DLL aligns DQ and DQS transitions with CK
transitions
•
Commands entered on each positive CK edge: data
and data mask referenced to both edges of DQS
•
Four internal banks for concurrent operation
•
Data mask (DM) for write data
•
Burst lengths: 4, 8
•
/CAS Latency (CL): 3, 4, 5
•
Auto precharge operation for each burst access
•
Auto refresh and self refresh modes
•
Average refresh period
7.8µs at 0°C
≤
TC
≤ +85°C
3.9µs at
+85°C <
TC
≤ +95°C
•
SSTL_18 compatible I/O
•
Posted CAS by programmable additive latency for
better command and data bus efficiency
•
Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
•
/DQS can be disabled for single-ended Data Strobe
operation.
•
FBGA (µBGA) package with lead free solder
(Sn-Ag-Cu)
RoHS compliant
Document No. E0705E20 (Ver. 2.0)
Date Published July 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida
Memory, Inc. 2005
ELPIDA [ ELPIDA MEMORY ]
