EDE5104AJBG, EDE5108AJBG, EDE5116AJBG
Pin Configurations
/xxx indicates active low signal.
60-ball FBGA
(×4/×8 organization)
1
A
VDD
NU/ /RDQS
VSS
B
C
VDDQ
D
(NC)*
(NC)*
84-ball FBGA
(×16 organization)
8
9
A
1
2
3
7
8
9
2
3
7
VSSQ /DQS VDDQ
DQS
VDDQ
DQ2
VSSDL
/RAS
/CAS
A2
A6
A11
NC
VSSQ
DQ0
VSSQ
CK
/CK
/CS
A0
A4
A8
A13
VSS
K
VDD
H
(NC)*
VDD
B
NC
VSS
VSSQ /UDQS VDDQ
UDQS VSSQ DQ15
VDDQ
DQ8
VDDQ
DQ6
DM/RDQS
(NC)*
VSSQ
(DM)*
DQ7
DQ14 VSSQ UDM
C
VDDQ
D
E
DQ9 VDDQ
DQ1 VDDQ
VSSQ
DQ3
VSS
/WE
VDDQ
(NC)*
DQ4
DQ5
DQ12 VSSQ DQ11
VDD
NC
VSSQ
VSS
LDM
DQ10 VSSQ DQ13
VSSQ /LDQS VDDQ
LDQS VSSQ
VDDQ
DQ2
VSSDL
/RAS
/CAS
A2
A6
A11
NC
DQ0
VSSQ
CK
/CK
/CS
A0
A4
A8
NC
VSS
VDD
DQ7
VDDQ
DQ5
VDD
ODT
EO
E
F
VDDL VREF
CKE
BA0
A10
A3
A7
G
H
J
NC
VSS
K
L
VDD
A12
VDD
F
ODT
G
DQ6
VDDQ
DQ4
J
BA1
A1
A5
A9
DQ1 VDDQ
VSSQ
DQ3
VSS
/WE
BA1
A1
A5
A9
VDDL VREF
CKE
L
NC
M
A10
N
VSS
A3
A7
P
BA0
Note: ( )* marked pins are for
×4
organization.
L
NC
(Top view)
od
Pr
R
VDD
A12
NC
(Top view)
Pin name
A0 to A13
BA0, BA1
DQ0 to DQ15
DQS, /DQS
UDQS, /UDQS
LDQS, /LDQS
RDQS, /RDQS
/CS
/RAS, /CAS, /WE
CKE
CK, /CK
DM
UDM, LDM
Function
Pin name
Function
ODT control
Address inputs
Bank select
ODT
VDD
VSS
Supply voltage for internal circuit
Ground for internal circuit
Supply voltage for DQ circuit
Data input/output
Differential data strobe
VDDQ
VSSQ
uc
Ground for DQ circuit
Input reference voltage
Supply voltage for DLL circuit
Ground for DLL circuit
No connection
Not usable
Differential data strobe for read
Chip select
Command input
Clock enable
Differential clock input
Write data mask
VREF
VDDL
VSSDL
NC*
NU*
1
2
t
Notes: 1. Not internally connected with die.
2. Don’t use other than reserved functions.
Data Sheet E1044E40 (Ver. 4.0)
3
ELPIDA [ ELPIDA MEMORY ]
