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EDJ1108BASE-DG-E 参数 Datasheet PDF下载

EDJ1108BASE-DG-E图片预览
型号: EDJ1108BASE-DG-E
PDF下载: 下载PDF文件 查看货源
内容描述: 1G位DDR3 SDRAM [1G bits DDR3 SDRAM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 148 页 / 1889 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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DATA SHEET
1G bits DDR3 SDRAM
EDJ1104BASE (256M words
×
4 bits)
EDJ1108BASE (128M words
×
8 bits)
EDJ1116BASE (64M words
×
16 bits)
Specifications
Density: 1G bits
Organization
32M words
×
4 bits
×
8 banks (EDJ1104BASE)
16M words
×
8 bits
×
8 banks (EDJ1108BASE)
8M words
×
16 bits
×
8 banks (EDJ1116BASE)
Package
78-ball FBGA (EDJ1104/1108BASE)
96-ball FBGA (EDJ1116BASE)
Lead-free (RoHS compliant)
Power supply: VDD, VDDQ
=
1.5V
±
0.075V
Data rate
1600Mbps/1333Mbps/1066Mbps/800Mbps (max.)
1KB page size (EDJ1104/1108BASE)
Row address: A0 to A13
Column address: A0 to A9, A11 (EDJ1104BASE)
A0 to A9 (EDJ1108BASE)
2KB page size (EDJ1116BASE)
Row address: A0 to A12
Column address: A0 to A9
Eight internal banks for concurrent operation
Interface: SSTL_15
Burst lengths (BL): 8 and 4 with Burst Chop (BC)
Burst type (BT):
Sequential (8, 4 with BC)
Interleave (8, 4 with BC)
/CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11
/CAS Write Latency (CWL): 5, 6, 7, 8
Precharge: auto precharge option for each burst
access
Driver strength: RZQ/7, RZQ/6 (RZQ = 240Ω)
Refresh: auto-refresh, self-refresh
Features
Double-data-rate architecture; two data transfers per
clock cycle
The high-speed data transfer is realized by the 8 bits
prefetch pipelined architecture
Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
Data mask (DM) for write data
Posted /CAS by programmable additive latency for
better command and data bus efficiency
On-Die Termination (ODT) for better signal quality
Synchronous ODT
Dynamic ODT
Asynchronous ODT
Multi Purpose Register (MPR) for temperature read
out
ZQ calibration for DQ drive and ODT
Programmable Partial Array Self-Refresh (PASR)
/RESET pin for Power-up sequence and reset
function
SRT range:
Normal/extended
Auto/manual self-refresh
Programmable Output driver impedance control
Refresh cycles
Average refresh period
7.8µs at 0°C
TC
≤ +85°C
3.9µs at
+85°C <
TC
≤ +95°C
Operating case temperature range
TC = 0°C to +95°C
Document No. E1128E60 (Ver. 6.0)
Date Published April 2009 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida
Memory, Inc. 2007-2009