EDJ1108BASE-DG-E 参数 Datasheet PDF下载

EDJ1104BASE, EDJ1108BASE, EDJ1116BASE

VREF Tolerances

The dc-tolerance limits and ac-noise limits for the reference voltages VREFCA and VREFDQ are shown in Figure

VREF(DC) Tolerance and VREF AC-Noise Limits. It shows a valid reference voltage VREF(t) as a function of time.

(VREF stands for VREFCA and VREFDQ likewise).

VREF(DC) is the linear average of VREF(t) over a very long period of time (e.g. 1 sec). This average has to meet the

min/max requirements in the table of(Single-Ended AC and DC Input Levels for Command and Address).

Furthermore VREF(t) may temporarily deviate from VREF(DC) by no more than +/- 1% VDD.

voltage

VDD

VREF AC-noise

VREF(DC)

VREF(t)

VREF(DC)max.

VDD/2

VREF(DC)min.

VSS

time

VREF(DC) Tolerance and VREF AC-Noise Limits

The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent

on VREF.

VREF shall be understood as VREF(DC), as defined in figure above, VREF(DC) Tolerance and VREF AC-Noise

Limits.

This clarifies that DC-variations of VREF affect the absolute voltage a signal has to reach to achieve a valid high or

low level and therefore the time to which setup and hold is measured. System timing and voltage budgets need to

account for VREF(DC) deviations from the optimum position within the data-eye of the input signals.

This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage

associated with VREF AC-noise. Timing and voltage effects due to ac-noise on VREF up to the specified limit (±1%

of VDD) are included in DRAM timings and their associated deratings.

Data Sheet E1128E60 (Ver. 6.0)

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