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EDJ8232B5MB-DJ-F 参数 Datasheet PDF下载

EDJ8232B5MB-DJ-F图片预览
型号: EDJ8232B5MB-DJ-F
PDF下载: 下载PDF文件 查看货源
内容描述: 8G位DDR3 SDRAM , DDP [8G bits DDR3 SDRAM, DDP]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 142 页 / 1199 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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DATA SHEET
8G bits DDR3 SDRAM, DDP
EDJ8232B5MB (256M words
32 bits)
Specifications
Density: 8G bits
Organization
32M words
32 bits
8 banks
Package
136-ball FBGA
DDP: 2 pieces of 4G bits chip sealed in one
package
Lead-free (RoHS compliant) and Halogen-free
Power supply: VDD, VDDQ
�½
1.5V
0.075V
Data rate
1600Mbps/1333Mbps (max.)
4KB page size
Row address: A0 to A14
Column address: A0 to A9
Eight internal banks for concurrent operation
Interface: SSTL_15
Burst lengths (BL): 8 and 4 with Burst Chop (BC)
Burst type (BT):
Sequential (8, 4 with BC)
Interleave (8, 4 with BC)
/CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11
/CAS Write Latency (CWL): 5, 6, 7, 8
Precharge: auto precharge option for each burst
access
Driver strength: RZQ/7, RZQ/6 (RZQ = 240)
Refresh: auto-refresh, self-refresh
Refresh cycles
Average refresh period
7.8s at 0C
TC
 85C
3.9s at
85C 
TC
 95C
Operating case temperature range
TC = 0C to +95C
Features
Double-data-rate architecture: two data transfers per
clock cycle
The high-speed data transfer is realized by the 8 bits
prefetch pipelined architecture
Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
Data mask (DM) for write data
Posted /CAS by programmable additive latency for
better command and data bus efficiency
On-Die Termination (ODT) for better signal quality
Synchronous ODT
Dynamic ODT
Asynchronous ODT
Multi Purpose Register (MPR) for pre-defined pattern
read out
ZQ calibration for DQ drive and ODT
Programmable Partial Array Self-Refresh (PASR)
/RESET pin for Power-up sequence and reset
function
SRT range:
Normal/extended
Programmable Output driver impedance control
Document No. E1825E30 (Ver. 3.0)
Date Published March 2012 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida
Memory, Inc. 2011-2012