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EDL1216AASA-75-E 参数 Datasheet PDF下载

EDL1216AASA-75-E图片预览
型号: EDL1216AASA-75-E
PDF下载: 下载PDF文件 查看货源
内容描述: 128M位的移动RAM [128M bits Mobile RAM]
分类和应用: 存储内存集成电路动态存储器
文件页数/大小: 59 页 / 470 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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DATA SHEET
128M bits Mobile RAM
EDL1216AASA (8M words
×
16 bits)
Description
The EDL1216AA is a 128M bits Mobile RAM organized
as 2,097,152 words
×
16 bits
×
4 banks. The Mobile
RAM achieved low power consumption and high-speed
data transfer using the pipeline architecture. All inputs
and outputs are synchronized with the positive edge of
the clock.
This product is packaged in 54-ball FBGA (µBGA
).
Pin Configurations
/xxx indicates active low signal.
54-ball FBGA ( BGA)
1
A
VSS
DQ15 VSSQ
VDDQ
DQ0
VDD
2
3
4
5
6
7
8
9
B
Features
Low voltage power supply
VDD:
2.5V
±
0.2V
VDDQ: 1.8V
±
0.15V
Wide temperature range (−25°C to 85°C)
Programmable partial self refresh
Programmable driver strength
Programmable temperature compensated self refresh
(Option)
Deep power down mode
Small package (54-ball FBGA (µBGA))
Fully Synchronous Dynamic RAM, with all signals
referenced to a positive clock edge
Pulsed interface
Possible to assert random column address in every
cycle
Quad internal banks controlled by BA0 and BA1
Byte control by LDQM and UDQM
Wrap sequence = Sequential/ Interleave
/CAS latency (CL) = 2, 3
Automatic precharge and controlled precharge
Auto refresh and self refresh
• ×16
organization
4,096 refresh cycles/64ms
Burst termination by Burst stop command and
Precharge command
FBGA(µBGA) package is lead free solder (Sn-Ag-Cu)
C
DQ14 DQ13 VDDQ
VSSQ
DQ2
DQ1
DQ12 DQ11 VSSQ
VDDQ
DQ4
DQ3
D
DQ10
DQ9
VDDQ
VSSQ
DQ6
DQ5
E
DQ8
NC
VSS
VDD
LDQM
DQ7
F
UDQM
CLK
CKE
/CAS
/RAS
/WE
G
NC
A11
A9
BA0
BA1
/CS
H
A8
A7
A6
A0
A1
A10
J
VSS
A5
A4
A3
A2
VDD
(Top view)
Applications
Mobile cellular handsets, PDAs, wireless PDAs,
handheld PCs, home electronic appliances, and
information appliances, etc.
A0 to A11
BA0, BA1
DQ0 to DQ15
CLK
CKE
/CS
/RAS
/CAS
/WE
UDQM
LDQM
VDD
VSS
VDDQ
VSSQ
NC
Address inputs
Bank select
Data inputs/ outputs
Clock input
Clock enable
Chip select
Row address strobe
Column address strobe
Write enable
Upper DQ mask enable
Lower DQ mask enable
Power supply
Ground
Power supply for DQ
Ground for DQ
No connection
Document No. E0196E30 (Ver. 3.0)
Date Published June 2002 (K) Japan
URL: http://www.elpida.com
Elpida
Memory, Inc. 2001-2002