PRELIMINARY DATA SHEET
64M bits Mobile RAM
EDL6416CBBH (4M words
×
16 bits)
Specifications
•
Density: 64M bits
•
Organization: 1M words
×
16 bits
×
4 banks
•
Package: 60-ball FBGA
Lead-free (RoHS compliant) and Halogen-free
•
Power supply: VDD, VDDQ
=
1.7V to 1.95V
•
Clock frequency: 133MHz (max.)
•
1KB page size
Row address: A0 to A11
Column address: A0 to A7
•
Four internal banks for concurrent operation
•
Interface: LVCMOS
•
Burst lengths (BL): 1, 2, 4, 8, full page
•
Burst type (BT):
Sequential (1, 2, 4, 8, full page)
Interleave (1, 2, 4, 8)
•
/CAS Latency (CL): 3
•
Precharge: auto precharge option for each burst
access
•
Driver strength: normal/weak
•
Refresh: auto-refresh, self-refresh
•
Refresh cycles: 4096 cycles/64ms
Average refresh period: 15.6µs
•
Operating ambient temperature range
TA = –25°C to +85°C
Pin Configurations
/xxx indicates active low signal.
60-ball FBGA
1
2
3
4
5
6
7
8
9
10
A
VSS
DQ15
VSSQ
VDDQ
DQ0
VDD
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
NC
B
VDDQ
DQ13
DQ14
C
VSSQ
DQ11
DQ12
D
VDDQ
DQ9
DQ10
E
NC
NC
DQ8
F
VSS
UDQM
NC
NC
LDQM
VDD
G
CKE
CLK
NC
/WE
/CAS
/RAS
/CS
H
A9
A11
A7
A4
NC
A8
A5
BA0
BA1
A1
VDD
J
A6
A10/AP
A0
K
VSS
A2
A3
(Top view)
A0 to A11
BA0, BA1
DQ0 to DQ15
CLK
CKE
/CS
/RAS
/CAS
/WE
UDQM
LDQM
VDD
VSS
VDDQ
VSSQ
NC
Address inputs
Bank select
Data inputs/ outputs
Clock input
Clock enable
Chip select
Row address strobe
Column address strobe
Write enable
Upper DQ mask enable
Lower DQ mask enable
Power supply
Ground
Power supply for DQ
Ground for DQ
No connection
Features
•
•
•
•
•
•
Low power consumption
Single pulsed /RAS
Burst read/write operation capability
Byte control by DQM
Programmable Partial Array Self-Refresh
Auto Temperature Compensated Self-Refresh
(ATCSR) by built-in temperature sensor
•
Burst termination by burst stop command and
Precharge command
Document No. E1138E21 (Ver. 2.1)
Date Published August 2008 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida
Memory, Inc. 2007-2008
ELPIDA [ ELPIDA MEMORY ]
