PRELIMINARY DATA SHEET
128M bits SDRAM
EDS1216AGTA (8M words
×
16 bits)
Specifications
•
Density: 128M bits
•
Organization
2M words
×
16 bits
×
4 banks
•
Package: 54-pin plastic TSOP (II)
Lead-free (RoHS compliant)
•
Power supply: VDD, VDDQ
=
3.3V
±
0.3V
•
Clock frequency: 166MHz/133MHz (max.)
•
Four internal banks for concurrent operation
•
Interface: LVTTL
•
Burst lengths (BL): 1, 2, 4, 8, full page
•
Burst type (BT):
Sequential (1, 2, 4, 8, full page)
Interleave (1, 2, 4, 8)
•
/CAS Latency (CL): 2, 3
•
Precharge: auto precharge option for each burst
access
•
Refresh: auto-refresh, self-refresh
•
Refresh cycles: 4096 cycles/64ms
Average refresh period: 15.6µs
•
Operating ambient temperature range
TA = 0°C to +70°C
Pin Configurations
/xxx indicates active low signal.
54-pin Plastic TSOP (II)
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
Features
•
Single pulsed /RAS
•
Burst read/write operation and burst read/single write
operation capability
•
Byte control by UDQM and LDQM
DQ7
VDD
LDQM
/WE
/CAS
/RAS
/CS
BA0
BA1
A10
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VSS
(Top view)
A0 to A11
BA0, BA1
DQ0 to DQ15
/CS
/RAS
/CAS
/WE
LDQM, UDQM
CKE
CLK
VDD
VSS
VDDQ
VSSQ
NC
Address input
Bank select address
Data-input/output
Chip select
Row address strobe
Column address strobe
Write enable
Input/output mask
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Document No. E0847E20 (Ver. 2.0)
Date Published February 2006 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida
Memory, Inc. 2005-2006
ELPIDA [ ELPIDA MEMORY ]
