DATA SHEET
128M bits SDRAM
EDS1216AABH, EDS1216CABH
(8M words
×
16 bits)
Description
The EDS1216AABH, EDS1216CABH are 128M bits
SDRAM organized as 2,097,152 words
×
16 bits
×
4
banks. All inputs and outputs are synchronized with
the positive edge of the clock.
Supply voltages are 3.3V (EDS1216AABH) and 2.5V
(EDS1216CABH).
They are packaged in 54-ball FBGA.
Pin Configurations
/xxx indicate active low signal.
54-ball FBGA
1
A
VSS
DQ15
VSSQ
VDDQ
DQ0
VDD
2
3
4
5
6
7
8
9
B
DQ14
DQ13
VDDQ
VSSQ
DQ2
DQ1
Features
•
•
•
•
•
3.3V and 2.5V power supply
Clock frequency: 133MHz (max.)
Single pulsed /RAS
×16
organization
4 banks can operate simultaneously and
independently
•
Burst read/write operation and burst read/single
write operation capability
•
Programmable burst length (BL): 1, 2, 4, 8, full page
•
2 variations of burst sequence
Sequential (BL = 1, 2, 4, 8, full page)
Interleave (BL = 1, 2, 4, 8)
•
Programmable /CAS latency (CL): 2, 3
•
Byte control by UDQM and LDQM
•
Refresh cycles: 4096 refresh cycles/64ms
•
2 variations of refresh
Auto refresh
Self refresh
•
FBGA package with lead free solder (Sn-Ag-Cu)
C
DQ12
DQ11
VSSQ
VDDQ
DQ4
DQ3
D
DQ10
DQ9
VDDQ
VSSQ
DQ6
DQ5
E
DQ8
NC
VSS
VDD
LDQM
DQ7
F
UDQM
CLK
CKE
/CAS
/RAS
/WE
G
NC
A11
A9
BA0
BA1
/CS
H
A8
A7
A6
A0
A1
A10
J
VSS
A5
A4
A3
A2
VDD
(Top view)
A0 to A11
BA0, BA1
DQ0 to DQ15
CLK
CKE
/CS
/RAS
/CAS
/WE
LDQM /UDQM
VDD
VSS
VDDQ
VSSQ
NC
Address inputs
Bank select
Data inputs/ outputs
Clock input
Clock enable
Chip select
Row address strobe
Column address strobe
Write enable
Input/output mask
Power supply
Ground
Power supply for DQ
Ground for DQ
No connection
Document No. E0410E40 (Ver. 4.0)
Date Published February 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida
Memory, Inc. 2003-2005
ELPIDA [ ELPIDA MEMORY ]
