EDS1216AABH, EDS1216CABH
AC Characteristics (TA = 0 to +70°C, VDD, VDDQ = 3.3V ± 0.3V, VSS, VSSQ = 0V) [EDS1216AA]
(TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V) [EDS1216CA]
-75
Parameter
System clock cycle time
(CL = 2)
(CL = 3)
CLK high pulse width
CLK low pulse width
Access time from CLK
(CL = 2)
(CL = 3)
Data-out hold time
CLK to Data-out low impedance
CLK to Data-out high impedance
(CL = 2)
(CL = 3)
Input setup time
Input hold time
Ref/Active to Ref/Active command
period
Active to Precharge command
period
Active command to column
command (same bank)
Precharge to active command
period
Write recovery or data-in to
precharge lead time
Last data into active latency
Active (a) to Active (b) command
period
Transition time (rise and fall)
Refresh period
(4096 refresh cycles)
Symbol
tCK
tCK
tCH
tCL
tAC
tAC
tOH
tLZ
tHZ
tHZ
tSI
tHI
tRC
tRAS
tRCD
tRP
tDPL
tDAL
tRRD
tT
tREF
min.
10
7.5
2.5
2.5
—
—
2.0
0
—
—
1.5
0.8
67.5
45
20
20
15
2CLK + 20ns
15
0.5
—
max.
—
—
—
—
6
5.4
—
—
6
5.4
—
—
—
120000
—
—
—
—
—
5
64
ns
ns
ms
1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
Notes
1
1
1
1
1, 2
1, 2
1, 2
1, 2, 3
1, 4
1, 4
1
1
1
1
1
1
1
Notes: 1. AC measurement assumes tT = 0.5ns. Reference level for timing of input signals is 1.4V(EDS1216AA)
and 1.2V (EDS1216CA).
2. Access time is measured at 1.4V(EDS1216AA) and 1.2V (EDS1216CA). Load condition is CL = 30pF.
3. tLZ (min.) defines the time at which the outputs achieves the low impedance state.
4. tHZ (max.) defines the time at which the outputs achieves the high impedance state.
Data Sheet E0410E40 (Ver. 4.0)
7
ELPIDA [ ELPIDA MEMORY ]
