EDS1232CABB, EDS1232CATA
Pin Capacitance (TA = 25°C, f = 1MHz)
90-ball FBGA
Parameter
Input capacitance
Symbol Pins
CI1
CI2
Data input/output
capacitance
CI/O
Address
min.
1.5
Typ
—
—
—
max.
3.0
3.0
5.5
86-pin TSOP (II)
min.
2.5
2.5
4.0
Typ
—
—
—
max.
4.0
4.0
6.5
Unit
pF
pF
pF
Notes
CLK, CKE, /CS, /RAS,
1.5
/CAS, /WE, DQM
DQ
3.0
AC Characteristics (TA = 0 to +70°C, VDD, VDDQ = 2.5V±0.2V, VSS, VSSQ = 0V)
°
±
-75
Parameter
System clock cycle time
(CL = 2)
(CL = 3)
CLK high pulse width
CLK low pulse width
Access time from CLK
Data-out hold time
CLK to Data-out low impedance
CLK to Data-out high impedance
Input setup time
Input hold time
CKE setup time (Power down exit)
ACT to REF/ACT command period
(operation)
(refresh)
Active to Precharge command period
Active command to column command
(same bank)
Precharge to active command period
Write recovery or data-in to precharge
lead time
Last data into active latency
Symbol
tCK
tCK
tCH
tCL
tAC
tOH
tLZ
tHZ
tSI
tHI
tCKSP
tRC
tRC
tRAS
tRCD
tRP
tDPL
tDAL
min.
10
7.5
2.5
2.5
—
2
0
2
1.5
0.8
1.5
67.5
67.5
45
20
20
15
2CLK +
20ns
15
2
0.5
—
max.
—
—
—
—
5.4
—
—
5.4
—
—
—
120000
30
64
-1A
min.
10
10
3
3
—
2
0
2
2
1
2
70
70
50
20
20
20
2CLK +
20ns
20
2
0.5
—
max.
—
—
—
—
6
—
—
6
—
—
—
120000
—
—
30
64
ns
CLK
ns
ms
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Active (a) to Active (b) command period tRRD
Mode register set cycle time
Transition time (rise and fall)
Refresh period
(4096 refresh cycles)
tRSC
tT
tREF
Preliminary Data Sheet E0247E40 (Ver. 4.0)
7
ELPIDA [ ELPIDA MEMORY ]
