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EDS12322GBH-6DTT-F 参数 Datasheet PDF下载

EDS12322GBH-6DTT-F图片预览
型号: EDS12322GBH-6DTT-F
PDF下载: 下载PDF文件 查看货源
内容描述: 128M位的SDRAM WTR (宽温度范围) [128M bits SDRAM WTR (Wide Temperature Range)]
分类和应用: 存储内存集成电路动态存储器
文件页数/大小: 51 页 / 738 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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EDS12322GBH-TT
AC Characteristics (TA = –20°C to +85°C, VDD, VDDQ = 1.7V to 1.9V, VSS, VSSQ = 0V)
-6D
Parameter
System clock cycle time
CLK high pulse width
CLK low pulse width
Access time from CLK
Data-out hold time
CLK to Data-out low impedance
CLK to Data-out high impedance
Input setup time
Input hold time
Active to Ref/Active command period
Refresh to Ref/Active command period
Self-refresh exit to Ref/Active command period
Active to Precharge command period
Active command to column command (same bank)
Precharge to active command period
Write recovery or data-in to precharge lead time
Last data into active latency
Active (a) to Active (b) command period
Mode register set to active command period
Transition time (rise and fall)
Refresh period
(4096 refresh cycles)
Symbol
tCK
tCH
tCL
tAC
tOH
tLZ
tHZ
tSI
tHI
tRC
tRFC
tSREX
tRAS
tRCD
tRP
tDPL
tDAL
tRRD
tMRD
tT
tREF
min.
6
2.5
2.5
2.5
0
1.5
0.8
67.5
80
120
45
18
18
15
2CLK +
tRP
15
2
0.5
max.
5.4
5.4
120000
1.0
64
-7B
min.
7.5
2.5
2.5
2.5
0
1.5
0.8
67.5
80
120
45
22.5
22.5
15
2CLK +
tRP
15
2
0.5
max.
6.0
6.0
120000
1.0
64
ns
tCK
ns
ms
1
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1
1, 5
1, 5
1, 2, 5
1, 2, 5
1, 2, 3, 5
1, 4
1, 5
1, 5
1
1
1
1
1
1
1
Notes: 1.
2.
3.
4.
5.
AC measurement assumes tT = 0.5ns. Reference level for timing of input signals is 0.5
×
VDDQ.
Access time is measured at 0.5
×
VDDQ. Load condition is CL = 30pF.
tLZ (min.) defines the time at which the outputs achieves the low impedance state.
tHZ (max.) defines the time at which the outputs achieves the high impedance state.
If tT
1ns, each parameters is changed as follows;
tAC, tOH, tLZ: should be added (tT (rise)/2 – 0.5)
tCH, tCL, tSI, tHI: should be added {(tT (rise) + tT (fall))/2 – 1}
Test Conditions
Input and output timing reference levels: VDDQ
×
0.5
Input waveform and output load: See following figures
1.6V
input
0.2V
1.4V
0.3V
I/O
CL
t
T
tT
Output load
Preliminary Data Sheet E1347E20 (Ver. 2.0)
8