DATA SHEET
128M bits SDRAM
EDS1232AHTA (4M words
×
32 bits)
Specifications
•
Density: 128M bits
•
Organization
⎯
1M words
×
32 bits
×
4 banks
•
Package: 86-pin plastic TSOP (II)
⎯
Lead-free (RoHS compliant)
•
Power supply: VDD, VDDQ
=
3.3V
±
0.3V
•
Clock frequency: 166MHz/133MHz (max.)
•
Four internal banks for concurrent operation
•
Interface: LVTTL
•
Burst lengths (BL): 1, 2, 4, 8, full page
•
Burst type (BT):
⎯
Sequential (1, 2, 4, 8, full page)
⎯
Interleave (1, 2, 4, 8)
•
/CAS Latency (CL): 2, 3
•
Precharge: auto precharge option for each burst
access
•
Refresh: auto-refresh, self-refresh
•
Refresh cycles: 4096 cycles/64ms
⎯
Average refresh period: 15.6μs
•
Operating ambient temperature range
⎯
TA = 0°C to +70°C
Pin Configurations
/xxx indicates active low signal.
86-pin Plastic TSOP(II)
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDD
DQM0
/WE
/CAS
/RAS
/CS
A11
BA0
BA1
A10(AP)
A0
A1
A2
DQM2
VDD
NC
DQ16
VSSQ
DQ17
DQ18
VDDQ
DQ19
DQ20
VSSQ
DQ21
DQ22
VDDQ
DQ23
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
(Top view)
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSS
DQM1
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
VSS
NC
DQ31
VDDQ
DQ30
DQ29
VSSQ
DQ28
DQ27
VDDQ
DQ26
DQ25
VSSQ
DQ24
VSS
Features
• ×32
organization
•
Single pulsed /RAS
•
Burst read/write operation and burst read/single write
operation capability
•
Byte control by DQM
A0 to A11
BA0, BA1
DQ0 to DQ31
/CS
/RAS
/CAS
/WE
DQM0 to DQM3
Address inputs
Bank select
Data input/output
Chip select
Row address strobe
Column address strobe
CKE
CLK
VDD
VSS
VDDQ
VSSQ
Write enable
DQ mask enable
Clock enable
Clock input
Supply voltage
Ground
Supply voltage
for DQ
NC
Ground for DQ
No connection
Document No. E1163E30 (Ver. 3.0)
Date Published January 2008 (K) Japan
Printed in Japan
URL: http://www.elpida.com
©Elpida
Memory, Inc. 2007-2008