EDS1232AHTA
Function Truth Table
The following table shows the operations that are performed when each command is issued in each mode of the
SDRAM.
The following table assumes that CKE is high.
Current state
Precharge
/CS
H
L
L
L
L
L
L
L
L
Idle
H
L
L
L
L
L
L
L
L
Row active
H
L
L
L
L
L
L
L
L
Read
H
L
L
L
L
L
L
L
L
/RAS
×
H
H
H
H
L
L
L
L
×
H
H
H
H
L
L
L
L
×
H
H
H
H
L
L
L
L
×
H
H
H
H
L
L
L
L
/CAS
×
H
H
L
L
H
H
L
L
×
H
H
L
L
H
H
L
L
×
H
H
L
L
H
H
L
L
×
H
H
L
L
H
H
L
L
/WE
×
H
L
H
L
H
L
H
L
×
H
L
H
L
H
L
H
L
×
H
L
H
L
H
L
H
L
×
H
L
H
L
H
L
H
L
Address
×
×
×
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
×
MODE
×
×
×
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
×
MODE
×
×
×
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
×
MODE
×
×
×
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
×
MODE
Command
DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE, PALL
REF, SELF
MRS
DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE, PALL
REF, SELF
MRS
DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE, PALL
REF, SELF
MRS
DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE, PALL
REF, SELF
MRS
Operation
Enter IDLE after tRP
Enter IDLE after tRP
ILLEGAL
ILLEGAL*
ILLEGAL*
ILLEGAL*
NOP*
5
3
3
3
ILLEGAL
ILLEGAL
NOP
NOP
ILLEGAL
ILLEGAL*
ILLEGAL*
4
4
Bank and row active
NOP
Refresh
Mode register set*
NOP
NOP
ILLEGAL
Begin read*
6
6
8
Begin write*
Other bank active
2
ILLEGAL on same bank*
Precharge*
ILLEGAL
ILLEGAL
Continue burst to end
Continue burst to end
Burst stop
Continue burst read to /CAS
latency and New read
Term burst read/start write
Other bank active
2
ILLEGAL on same bank*
Term burst read and Precharge
ILLEGAL
ILLEGAL
7
Data Sheet E1163E30 (Ver. 3.0)
16
ELPIDA [ ELPIDA MEMORY ]
