DATA SHEET
16M bits SDRAM
EDS1616AGTA (1M words
×
16 bits)
Description
The EDS1616AGTA is 16M bits SDRAM organized as
524,288 words
×
16 bits
×
2 banks. All inputs and
outputs are synchronized with the positive edge of the
clock.
It is packaged in 50-pin plastic TSOP (II).
Pin Configurations
/xxx indicate active low signal.
50-pin Plastic TSOP (II)
VDD
DQ0
DQ1
VSSQ
DQ2
DQ3
VDDQ
DQ4
DQ5
VSSQ
DQ6
DQ7
VDDQ
LDQM
/WE
/CAS
/RAS
/CS
BA
A10
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
Features
•
•
•
•
•
3.3V power supply
Clock frequency: 166MHz/133MHz (max.)
Single pulsed /RAS
×16
organization
2 banks can operate simultaneously and
independently
•
Burst read/write operation and burst read/single
write operation capability
•
Programmable burst length (BL): 1, 2, 4, 8 and full
page
•
2 variations of burst sequence
Sequential (BL = 1, 2, 4, 8, full page)
Interleave (BL = 1, 2, 4, 8)
•
Programmable /CAS latency (CL): 2, 3
•
Byte control by UDQM and LDQM
•
Refresh cycles: 2048 refresh cycles/32ms
•
2 variations of refresh
Auto refresh
Self refresh
•
TSOP (II) package with lead free solder (Sn-Bi)
VSS
DQ15
DQ14
VSSQ
DQ13
DQ12
VDDQ
DQ11
DQ10
VSSQ
DQ9
DQ8
VDDQ
NC
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
VSS
(Top view)
A0 to A10
BA
DQ0 to DQ15
/CS
/RAS
/CAS
/WE
LDQM, UDQM
CKE
CLK
VDD
VSS
VDDQ
VSSQ
NC
Address input
Bank select address
Data-input/output
Chip select
Row address strobe
Column address strobe
Write enable
Input/output mask
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Document No. E0504E40 (Ver. 4.0)
Date Published June 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida
Memory, Inc. 2004-2005
ELPIDA [ ELPIDA MEMORY ]
