PRELIMINARY DATA SHEET
16M bits SDRAM
EDS1616GGBH (1M words
×
16 bits)
Specifications
•
Density: 16M bits
•
Organization
⎯
512K words
×
16 bits
×
2 banks
•
Package: 60-ball FBGA
⎯
Lead-free (RoHS compliant)
•
Power supply: VDD, VDDQ
=
3.3V
±
0.3V
•
Clock frequency: 100MHz (max.)
•
Two internal banks for concurrent operation
•
Interface: LVTTL
•
Burst lengths (BL): 1, 2, 4, 8, full page
•
Burst type (BT):
⎯
Sequential (1, 2, 4, 8, full page)
⎯
Interleave (1, 2, 4, 8)
•
/CAS Latency (CL): 2, 3
•
Precharge: auto precharge operation for each burst
access
•
Refresh: auto-refresh, self-refresh
•
Refresh cycles: 2048 cycles/32ms
⎯
Average refresh period: 15.6μs
•
Operating ambient temperature range
⎯
TA = 0°C to +70°C
Pin Configurations
/xxx indicates active low signal.
60-ball FBGA
1
A
VSS
B
DQ14
C
DQ13 VDDQ
D
DQ12
E
DQ10
F
DQ9
G
DQ8
H
J
NC
NC
DQ7
VDDQ
VSSQ
DQ6
VSSQ
VDDQ
DQ5
DQ11
DQ4
DQ3
VSSQ
DQ2
VSSQ
VDDQ
DQ1
DQ15
DQ0
VDD
2
3
4
5
6
7
EO
Features
•
Single pulsed /RAS
•
Burst read/write operation and burst read/single write
operation capability
•
Byte control by UDQM and LDQM
•
tDPL
=
1CLK
Document No. E0682E20 (Ver. 2.0)
Date Published December 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
L
od
Pr
NC
NC
NC
UDQM
K
L
NC
CLK
CKE
NC
M
BA
A9
N
A8
A7
P
A6
A5
R
VSS
A4
NC
NC
LDQM
/WE
/RAS
/CAS
NC
/CS
NC
NC
A0
A10
A2
A1
A3
VDD
A0 to A10
BA
DQ0 to DQ15
/CS
/RAS
/CAS
/WE
LDQM, UDQM
Address input
Bank select address
Data-input/output
Chip select
Row address strobe
Column address strobe
Write enable
Input/output mask
This product became EOL in March, 2007.
©Elpida
Memory, Inc. 2005
t
uc
(Top view)
CKE
CLK
VDD
VSS
VDDQ
VSSQ
NC
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
ELPIDA [ ELPIDA MEMORY ]
