EDS2504APTA/08APTA/16APTA-TI
Pin Function
CLK (input pin)
CLK is the master clock input to this pin. The other input signals are referred at CLK rising edge.
/CS (input pin)
When /CS is Low, the command input cycle becomes valid. When /CS is High, all inputs are ignored. However,
internal operations (bank active, burst operations, etc.) are held.
/RAS, /CAS, and /WE (input pins)
Although these pin names are the same as those of conventional DRAMs, they function in a different way. These
pins define operation commands (read, write, etc.) depending on the combination of their voltage levels. For details,
refer to the command operation section.
A0 toA12 (input pins)
Row address (AX0 to AX12) is determined by A0 to A12 at the bank active command cycle CLK rising edge.
Column address is determined by A0 to A8, A9 or A11 (see Address Pins Table) at the read or write command cycle
CLK rising edge. And this column address becomes burst access start address.
[Address Pins Table]
Address (A0 to A12)
Part number
EDS2504AP
EDS2508AP
EDS2516AP
Row address
AX0 to AX12
AX0 to AX12
AX0 to AX12
Column address
AY0 to AY9, AY11
AY0 to AY9
AY0 to AY8
A10 defines the precharge mode. When A10 = High at the precharge command cycle, all banks are precharged.
But when A10 = Low at the precharge command cycle, only the bank that is selected by BA0 and BA1 (BS) is
precharged. For details refer to the command operation section.
BA0 and BA1 (input pin)
BA0 and BA1 are bank select signal (BS). (See Bank Select Signal Table)
[Bank Select Signal Table]
BA0
Bank 0
Bank 1
Bank 2
Bank 3
L
H
L
H
BA1
L
L
H
H
Remark: H: VIH. L: VIL.
×:
VIH or VIL
CKE (input pin)
This pin determines whether or not the next CLK is valid. If CKE is High, the next CLK rising edge is valid. If CKE is
Low, the next CLK rising edge is invalid. This pin is used for power-down mode, clock suspend mode and self
refresh mode.
Preliminary Data Sheet E0248E10 (Ver. 1.0)
13
ELPIDA [ ELPIDA MEMORY ]
