PRELIMINARY DATA SHEET
256M bits SDRAM
EDS2516CDTA (16M words
×
16 bits)
Description
The EDS2516CDTA is 256M bits SDRAMs organized
as 4,194,304 words
×
16 bits
×
4 banks. All inputs and
outputs are synchronized with the positive edge of the
clock.
They are packaged in 54-pin plastic TSOP (II).
Pin Configurations
/xxx indicate active low signal.
54-pin Plastic TSOP (II)
VDD
DQ0
VDDQ
Features
•
•
•
•
•
2.5V power supply
Clock frequency: 133MHz (max.)
Single pulsed /RAS
×16
organization
4 banks can operate simultaneously and
independently
•
Burst read/write operation and burst read/single
write operation capability
•
2 variations of burst sequence
Sequential (BL = 1, 2, 4, 8, full page)
Interleave (BL = 1, 2, 4, 8)
•
Programmable /CAS latency (CL): 2, 3
•
Byte control by UDQM and LDQM
•
Refresh cycles: 8192 refresh cycles/64ms
•
2 variations of refresh
Auto refresh
Self refresh
•
TSOP (II) package with lead free solder (Sn-Bi)
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
LDQM
/WE
/CAS
/RAS
/CS
BA0
BA1
A10
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
NC
UDQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
VSS
(Top view)
A0 to A12
BA0, BA1
DQ0 to DQ15
/CS
/RAS
/CAS
/WE
UDQM,LDQM
Address input
Bank select address
Data-input/output
Chip select
Row address strobe
Column address strobe
CKE
CLK
VDD
VSS
VDDQ
VSSQ
Write enable
Input/output mask
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
NC
Power for DQ circuit
Ground for DQ circuit
No connection
Document No. E0545E40 (Ver. 4.0)
Date Published March 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida
Memory, Inc. 2004-2005
ELPIDA [ ELPIDA MEMORY ]
