DATA SHEET
256M bits SDRAM
EDS2508APSA (32M words
×
8 bits)
EDS2516APSA (16M words
×
16 bits)
Description
The EDS2508AP is a 256M bits SDRAM organized as
8,388,608 words
×
8 bits
×
4 banks. The EDS2516AP
is a 256M bits SDRAM organized as 4194304 words
×
16 bits
×
4 banks. All inputs and outputs are referred to
the rising edge of the clock input. It is packaged in
standard 60-ball
µBGA
.
Pin Configurations
/xxx indicates active low signal.
1
A
VSS
DQ15
(DQ7)*
DQ0
VDD
2
3
4
5
6
B
DQ14 VSSQ
(NC)*
VDDQ
DQ1
(NC)*
DQ2
(DQ1)*
Features
•
•
•
•
•
3.3V power supply
Clock frequency: 133MHz (max.)
LVTTL interface
Single pulsed /RAS
4 banks can operate simultaneously and
independently
•
Burst read/write operation and burst read/single write
operation capability
•
Programmable burst length (BL): 1, 2, 4, 8, full page
•
2 variations of burst sequence
Sequential (BL = 1, 2, 4, 8)
Interleave (BL = 1, 2, 4, 8)
•
Programmable /CAS latency (CL): 2, 3
•
Byte control by DQM
: DQM (EDS2508AP)
: UDQM, LDQM (EDS2516AP)
•
Refresh cycles: 8192 refresh cycles/64ms
•
2 variations of refresh
Auto refresh
Self refresh
C
D
DQ13 VDDQ
(DQ6)*
DQ12 DQ11
(NC)* (DQ5)*
VSSQ
DQ4
DQ3
(DQ2)* (NC)*
VDDQ
DQ5
(NC)*
DQ6
(DQ3)*
DQ7
(NC)*
NC
E
DQ10 VSSQ
(NC)*
F
DQ9 VDDQ
(DQ4)*
VSSQ
G
DQ8
(NC)*
NC
NC
H
NC
VSS
UDQM
(DQM)*
CLK
VDD
LDQM
(NC)*
/RAS
J
NC
/WE
K
L
NC
/CAS
CKE
A12
NC
/CS
M
A11
A9
BA1
BA0
N
A8
A7
A0
A10
P
A6
A5
A2
A1
R
VSS
A4
A3
VDD
(Top view)
Note: ( )* marked pins are for EDS2508APSA.
A0 to A12,
BA0, BA1
DQ0 to DQ15
/CS
/RAS
/CAS
/WE
Address input
Bank select address
Data-input/output
Chip select
Row address strobe
Column address strobe
Write enable
DQM
CKE
CLK
VDD
VSS
VDDQ
VSSQ
NC
Input/output mask
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Document No. E0228E30 (Ver. 3.0)
Date Published August 2002 (K) Japan
URL: http://www.elpida.com
Elpida
Memory, Inc.2001-2002
ELPIDA [ ELPIDA MEMORY ]
