EDS2508APSA, EDS2516APSA
Pin Capacitance (TA = 25°C, VDD, VDDQ = 3.3V ± 0.3V)
Parameter
Input capacitance
Symbol
CI1
CI2
Data input/output capacitance
CI/O
Pins
CLK
Address, CKE, /CS, /RAS,
/CAS, /WE, DQM,
DQ
min.
2.0
2.0
4
Typ
—
—
—
max.
3.5
3.8
6.5
Unit
pF
pF
pF
Notes
1, 2, 4
1, 2, 4
1, 2, 3, 4
Notes: 1.
2.
3.
4.
Capacitance measured with Boonton Meter or effective capacitance measuring method.
Measurement condition: f = 1MHz, 1.4V bias, 200mV swing.
DQM = VIH to disable DOUT.
This parameter is sampled and not 100% tested.
AC Characteristics (TA = 0 to +70°C, VDD, VDDQ = 3.3V ± 0.3V, VSS, VSSQ = 0V)
°
-7A
Parameter
System clock cycle time
CLK high pulse width
CLK low pulse width
Access time from CLK
Data-out hold time
CLK to Data-out low impedance
CLK to Data-out high impedance
Input setup time
Input hold time
Ref/Active to Ref/Active command
period
Active to Precharge command
period
Active command to column
command (same bank)
Precharge to active command
period
Write recovery or data-in to
precharge lead time
Last data into active latency
Active (a) to Active (b) command
period
Transition time (rise and fall)
Refresh period
(8192 refresh cycles)
Symbol
tCK
tCH
tCL
tAC
tOH
tLZ
tHZ
tSI
tHI
tRC
tRAS
tRCD
tRP
tDPL
tDAL
tRRD
tT
tREF
min.
7.5
2.5
2.5
—
3.0
1
—
1.5
0.8
60
45
15
15
15
2CLK +
15ns
15
0.5
—
max.
—
—
—
5.4
—
—
5.4
—
—
—
120000
—
—
—
—
—
5
64
-75
min.
7.5
2.5
2.5
—
3.0
1
—
1.5
0.8
67.5
45
20
20
15
2CLK +
20ns
15
0.5
—
max.
—
—
—
5.4
—
—
5.4
—
—
—
120000
—
—
—
—
—
5
64
ns
ns
ms
1
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1
1
1
1, 2
1, 2
1, 2, 3
1, 4
1
1
1
1
1
1
1
Notes: 1.
2.
3.
4.
AC measurement assumes tT = 0.5ns. Reference level for timing of input signals is 1.4V.
Access time is measured at 1.4V. Load condition is CL = 50pF.
tLZ (min.) defines the time at which the outputs achieves the low impedance state.
tHZ (max.) defines the time at which the outputs achieves the high impedance state.
Data Sheet E0228E30 (Ver. 3.0)
6
ELPIDA [ ELPIDA MEMORY ]
