EDS2508ADTA
DC Characteristics 1 (TA = 0 to +70°C, VDD, VDDQ = 3.3V ± 0.3V, VSS, VSSQ = 0V)
Parameter
Operating current
Standby current in power down
Standby current in power down
(input signal stable)
Standby current in non power down
Standby current in non power down
(input signal stable)
Active standby current in power down
Active standby current in power down
(input signal stable)
Symbol
IDD1
IDD2P
IDD2PS
IDD2N
IDD2NS
IDD3P
IDD3PS
Grade
max.
100
3
2
20
9
4
3
40
30
120
200
2
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Test condition
Burst length = 1
tRC = tRC (min.)
CKE = VIL,
tCK = tCK (min.)
CKE = VIL, tCK =
∞
CKE, /CS = VIH,
tCK = tCK (min.)
CKE = VIH, tCK =
∞,
/CS = VIH
CKE = VIL,
tCK = tCK (min.)
CKE = VIL, tCK =
∞
CKE, /CS = VIH,
tCK = tCK (min.)
CKE = VIH, tCK =
∞,
/CS = VIH
tCK = tCK (min.),
BL = 4
tRC = tRC (min.)
VIH
≥
VDD – 0.2V
VIL
≤
0.2V
Notes
1, 2, 3
6
7
4
8
1, 2, 6
2, 7
1, 2, 4
2, 8
1, 2, 5
3
EO
Burst operating current
Refresh current
Self refresh current
Active standby current in non power down IDD3N
Active standby current in non power down
IDD3NS
(input signal stable)
IDD4
IDD5
IDD6
Notes: 1. IDD depends on output load condition when the device is selected. IDD (max.) is specified at the output
open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CLK operating current.
7. After power down mode, no CLK operating current.
8. Input signals are VIH or VIL fixed.
Prelimimary Data Sheet E0633E10 (Ver. 1.0)
L
od
Pr
5
uc
t
ELPIDA [ ELPIDA MEMORY ]
