PRELIMINARY DATA SHEET
256M bits SDRAM
WTR (Wide Temperature Range)
EDS2516EEBH-TT (16M words
×
16 bits)
Description
The EDS2516EEBH is a 256M bits SDRAM organized
as 4,194,304 words
×
16 bits
×
4 banks. All inputs and
outputs are synchronized with the positive edge of the
clock.
It is packaged in 54-ball FBGA.
Pin Configurations
/xxx indicate active low signal.
54-ball FBGA
1
A
VSS
DQ15 VSSQ
VDDQ
DQ0
VDD
EO
Features
•
•
•
•
•
•
2
3
4
5
6
7
8
9
1.8V power supply
Clock frequency: 111MHz (max.)
LVCMOS interface
Single pulsed /RAS
×16
organization
4 banks can operate simultaneously and
independently
•
Burst read/write operation and burst read/single write
operation capability
•
Programmable burst length (BL): 1, 2, 4, 8 and full
page
•
2 variations of burst sequence
⎯
Sequential (BL = 1, 2, 4, 8, full page)
⎯
Interleave (BL = 1, 2, 4, 8)
•
Programmable /CAS latency (CL): 2, 3
•
Programmable driver strength: Half, Quarter
•
Byte control by UDQM and LDQM
•
Address
⎯
8K Row address /512 column address
•
Refresh cycles
•
8192 refresh cycles/64ms
•
2 variations of refresh
⎯
Auto refresh
⎯
Self refresh
•
Wide temperature range
⎯
Ambient temperature range:
−20°C
to +85°C
•
FBGA package with lead free solder (Sn-Ag-Cu)
⎯
RoHS compliant
B
DQ14 DQ13 VDDQ
VSSQ
DQ2
DQ1
C
DQ12 DQ11 VSSQ
VDDQ
DQ4
DQ3
D
DQ10
DQ9
VDDQ
VSSQ
DQ6
DQ5
Document No. E0800E10 (Ver. 1.0)
Date Published September 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
L
E
DQ8
NC
VSS
VDD
LDQM
DQ7
F
UDQM
CLK
CKE
/CAS
/RAS
/WE
G
A12
A11
A9
BA0
BA1
/CS
od
Pr
H
J
A8
A7
A6
VSS
A5
A4
A0
A1
A10
A3
A2
VDD
(Top view)
A0 to A12
BA0, BA1
DQ0 to DQ15
/CS
/RAS
/CAS
/WE
LDQM /UDQM
CKE
CLK
VDD
VSS
VDDQ
VSSQ
NC
Address inputs
Bank select address
Data input/ output
Chip select
Row address strobe
Column address strobe
Write enable
Input/output mask
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
This product became EOL in April, 2007.
©Elpida
Memory, Inc. 2005
t
uc
ELPIDA [ ELPIDA MEMORY ]
