EDS2516JEBH-75R3
Test Conditions
•
Input and output timing reference levels: 1.2V
•
Input waveform and output load: See following figures
2.1V
input
0.3V
1.7V
0.7V
I/O
CL
t
T
tT
Output load
Relationship Between Frequency and Minimum Latency
Parameter
-75R3
133
Symbol
lRCD
lRC
lRAS
lRP
lDPL
lRRD
lDAL
7.5
3
9
6
3
3
2
5
Unit
tCK
tCK
tCK
tCK
tCK
tCK
tCK
Note
1
1
1
1
1
1
= [lDPL +
lRP]
EO
Frequency (MHz)
tCK (ns)
DQM to data in
DQM to data out
CKE to CLK disable
/CS to command disable
Active command to column command
(same bank)
Active command to active command
(same bank)
Active command to precharge command
(same bank)
Precharge command to active command
(same bank)
Write recovery or data-in to precharge
command (same bank)
Active command to active command
(different bank)
Last data in to active command
(Auto precharge, same bank)
Precharge command to high impedance
(CL = 3)
Last data out to active command
(Auto precharge, same bank)
Last data out to precharge (early precharge)
(CL = 3)
Column command to column command
Write command to data in latency
Mode register set to active command
Power down exit to command input
Note: 1.
lRCD
to
lRRD
are recommended value.
Preliminary Data Sheet E0811E10 (Ver. 1.0)
L
od
Pr
lHZP
3
tCK
lAPR
lEP
1
tCK
–2
1
tCK
tCK
lCCD
lWCD
lDID
0
tCK
0
tCK
lDOD
lCLE
2
tCK
1
2
tCK
lMRD
lCDD
lPEC
tCK
0
tCK
1
tCK
uc
t
8
ELPIDA [ ELPIDA MEMORY ]
