EDS2532CABJ
Test Conditions
• Input and output timing reference levels: 1.2V
• Input waveform and output load: See following figures
2.1V
I/O
1.7V
input
0.7V
0.3V
CL
tT
tT
Output load
Relationship Between Frequency and Minimum Latency
Parameter
-75
133
7.5
-1A
100
10
Frequency (MHz)
tCK (ns)
Symbol
Unit
tCK
Notes
1
Active command to column command
(same bank)
lRCD
3
9
6
3
2
2
7
5
2
2
Active command to active command
(same bank)
lRC
tCK
tCK
tCK
tCK
1
1
1
1
Active command to precharge command
(same bank)
lRAS
lRP
Precharge command to active command
(same bank)
Write recovery or data-in to precharge
command (same bank)
lDPL
Active command to active command
(different bank)
lRRD
lSREX
lDAL
2
1
5
2
1
4
tCK
tCK
tCK
1
Self refresh exit time
2
Last data in to active command
(Auto precharge, same bank)
= [lDPL + lRP]
= [lRC]
3
Self refresh exit to command input
lSEC
9
7
tCK
Precharge command to high impedance
(CL = 2)
lHZP
lHZP
2
3
2
3
tCK
tCK
(CL = 3)
Last data out to active command
(Auto precharge, same bank)
lAPR
1
1
tCK
Last data out to precharge (early
precharge)
(CL = 2)
lEP
–1
–1
tCK
(CL = 3)
lEP
–2
1
–2
1
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
Column command to column command
Write command to data in latency
DQM to data in
lCCD
lWCD
lDID
0
0
0
0
DQM to data out
lDOD
lCLE
lMRD
lCDD
lPEC
2
2
CKE to CLK disable
1
1
Register set to active command
/CS to command disable
Power down exit to command input
2
2
0
0
1
1
Notes: 1. lRCD to lRRD are recommended value.
2. Be valid [DESL] or [NOP] at next command of self refresh exit.
3. Except [DESL] and [NOP]
Data Sheet E0460E40 (Ver. 4.0)
8
ELPIDA [ ELPIDA MEMORY ]
