EDS2532CABJ
AC Characteristics (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V)
-75
Parameter
System clock cycle time
(CL = 2)
(CL = 3)
CLK high pulse width
CLK low pulse width
Access time from CLK
Data-out hold time
CLK to Data-out low impedance
Symbol
tCK
tCK
tCH
tCL
tAC
tOH
tLZ
min.
10
7.5
2.5
2.5
—
2.0
0
—
1.5
0.8
67.5
45
20
20
15
max.
—
—
—
—
5.4
—
—
5.4
—
—
—
120000
—
—
—
-1A
min.
10
10
3
3
—
2.0
0
—
2
1
70
50
20
20
20
max.
—
—
—
—
6
—
—
6
—
—
—
120000
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1
1
1
1
1, 2
1, 2
1, 2, 3
1, 4
1
1
1
1
1
1
1
CLK to Data-out high impedance tHZ
Input setup time
Input hold time
tSI
tHI
tRC
tRAS
tRCD
tRP
EO
Last data into active latency
Transition time (rise and fall)
Refresh period
(4096 refresh cycles)
Ref/Active to Ref/Active
command period
Active to Precharge command
period
Active command to column
command (same bank)
Precharge to active command
period
Write recovery or data-in to
precharge lead time
Active (a) to Active (b) command
tRRD
period
tT
L
tDPL
tDAL
tREF
2CLK + 20ns —
15
0.5
—
—
5.0
64
2CLK + 20ns —
20
0.5
—
—
5
ns
ns
ms
1
od
Pr
64
Notes: 1.
2.
3.
4.
AC measurement assumes tT = 0.5ns. Reference level for timing of input signals is 1.2V.
Access time is measured at 1.2V. Load condition is CL = 30pF.
tLZ (min.) defines the time at which the outputs achieves the low impedance state.
tHZ (max.) defines the time at which the outputs achieves the high impedance state.
t
uc
Data Sheet E0460E40 (Ver. 4.0)
7
ELPIDA [ ELPIDA MEMORY ]
