DATA SHEET
256M bits SDRAM
EDS2532CASG (8M words
×
32 bits)
Specifications
•
Density: 256M bits
•
Organization
⎯
2M words
×
32 bits
×
4 banks
•
Package: 90-ball FBGA
⎯
Lead-free (RoHS compliant)
•
Power supply: VDD, VDDQ
=
2.5V
±
0.2V
•
Clock frequency: 133MHz/100MHz (max.)
•
2KB page size
⎯
Row address: A0 to A11
⎯
Column address: A0 to A8
•
Four internal banks for concurrent operation
•
Interface: LVTTL
•
Burst lengths (BL): 1, 2, 4, 8, full page
•
Burst type (BT):
⎯
Sequential (1, 2, 4, 8, full page)
⎯
Interleave (1, 2, 4, 8)
•
/CAS Latency (CL): 2, 3
•
Precharge: auto precharge operation for each burst
access
•
Refresh: auto-refresh, self-refresh
•
Refresh cycles: 4096 cycles/64ms
⎯
Average refresh period: 15.6μs
•
Operating ambient temperature range
⎯
TA = 0°C to +70°C
Pin Configurations
/xxx indicates active low signal.
90-ball FBGA
1
2
3
4
5
6
7
A
DQ13 VSS
VDD
VSS
VDD
DQ2
DQ4
DQ3
DQ6
VDD
EO
Features
B
DQ11 DQ15 VSSQ
VDDQ DQ0
VSSQ DQ1
VDDQ DQ5
VSSQ DQ7
VSS
/CS
NC
BA1
A1
C
DQ14 DQ12 VDDQ
D
DQ10 DQ9 VSSQ
E
DQ8
VDD VDDQ
F
VSS DQM1 VDD
/WE DQM0
/CAS /RAS
A11
A10
A2
BA0
A0
DQM2
• ×32
organization
•
Single pulsed /RAS
•
Burst read/write operation and burst read/single write
operation capability
•
Byte control by DQM
Document No. E0541E21 (Ver. 2.1)
Date Published February 2006 (K) Japan
Printed in Japan
URL: http://www.elpida.com
L
G
CLK
CKE
A8
A5
A9
A7
A4
H
NC
J
A6
K
A3
DQM3 VDD
od
Pr
L
VSS DQ31 VDDQ
VSSQ DQ16 VSS
M
N
P
DQ29 DQ30 VSSQ
VDDQ DQ17 DQ18
VSSQ DQ22 DQ20
DQ25 DQ27 VDDQ
DQ28 DQ24 VSSQ
DQ26 VSS
VDD
VDDQ DQ23 DQ19
VSS
VDD DQ21
R
(Top view)
Address inputs
Bank select address
Data-input/output
Chip select
Row address strobe
Column address strobe
Write enable
DQ mask enable
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
A0 to A11
BA0, BA1
DQ0 to DQ31
/CS
/RAS
/CAS
/WE
DQM0 to DQM3
CKE
CLK
VDD
VSS
VDDQ
VSSQ
NC
This product became EOL in March, 2007.
©Elpida
Memory, Inc. 2004-2006
t
uc
ELPIDA [ ELPIDA MEMORY ]
