EDS2532JEBH-75TT 参数 Datasheet PDF下载

EDS2532JEBH-75TT

Pin Function

CLK (input pin)

CLK is the master clock input. Other inputs signals are referenced to the CLK rising edge.

CKE (input pins)

CKE determine validity of the next CLK (clock). If CKE is high, the next CLK rising edge is valid; otherwise it is

invalid. If the CLK rising edge is invalid, the internal clock is not issued and the Synchronous DRAM suspends

operation.

When the Synchronous DRAM is not in burst mode and CKE is negated, the device enters power down mode.

During power down mode, CKE must remain low.

/CS (input pins)

/CS low starts the command input cycle. When /CS is high, commands are ignored but operations continue.

EO

[Address Pins Table]

Part number

EDS2532JEBH

Bank 0

Bank 1

Bank 2

Bank 3

/RAS, /CAS, and /WE (input pins)

/RAS, /CAS and /WE have the same symbols on conventional DRAM but different functions. For details, refer to the

command table.

A0 to A11 (input pins)

Row Address is determined by A0 to A11 at the CLK (clock) rising edge in the active command cycle.

Column Address is determined by A0 to A8 at the CLK rising edge in the read or write command cycle.

A10 defines the precharge mode. When A10 is high in the precharge command cycle, all banks are precharged;

when A10 is low, only the bank selected by BA0 and BA1 is precharged.

When A10 is high in read or write command cycle, the precharge starts automatically after the burst access.

BA0 and BA1 (input pin)

BA0 and BA1 are bank select signal (BS). (See Bank Select Signal Table)

[Bank Select Signal Table]

BA0

Remark: H: VIH. L: VIL.

DQM (input pins)

DQM controls I/O buffers. DQM0 controls DQ0 to DQ7, DQM1 controls DQ8 to DQ15, DQM2 controls DQ16 to

DQ23, DQM3 controls DQ24 to DQ31. In read mode, DQM controls the output buffers like a conventional /OE pin.

DQM high and DQM low turn the output buffers off and on, respectively. The DQM latency for the read is two clocks.

In write mode, DQM controls the word mask. Input data is written to the memory cell if DQM is low but not if DQM is

high. The DQM latency for the write is zero.

Data Sheet E0909E10 (Ver. 1.0)

L

L

H

L

H

Address (A0 to A11)

Row address

Column address

AY0 to AY8

AX0 to AX11

od

Pr

BA1

L

L

H

H

uc

t

10