DATA SHEET
256M bits SDRAM
EDS2732CABJ (8M words
×
32 bits)
Description
The EDS2732CA is a 256M bits SDRAM organized as
2,097,152 words
×
32 bits
×
4 banks. All inputs and
outputs are synchronized with the positive edge of the
clock.
It is packaged in 90-ball FBGA.
Pin Configurations
/xxx indicate active low signal.
90-ball FBGA
1
2
3
4
5
6
7
8
9
A
DQ26 DQ24 VSS
VDD DQ23 DQ21
VDDQ VSSQ DQ19
DQ22 DQ20 VDDQ
DQ17 DQ18 VDDQ
NC
A2
A10
NC
BA0
/CAS
VDD
DQ6
DQ1
DQ16 VSSQ
DQM2 VDD
A0
BA1
/CS
A1
A11
/RAS
EO
Features
•
•
•
•
•
B
DQ28 VDDQ VSSQ
2.5V power supply
Clock frequency: 133MHz/100MHz (max.)
Single pulsed /RAS
×32
organization
4 banks can operate simultaneously and
independently
•
Burst read/write operation and burst read/single write
operation capability
•
Programmable burst length (BL): 1, 2, 4, 8 and full
page
•
2 variations of burst sequence
⎯
Sequential (BL = 1, 2, 4, 8, full page)
⎯
Interleave (BL = 1, 2, 4, 8)
•
Programmable /CAS latency (CL): 2, 3
•
Byte control by DQM
•
Address
⎯
8K Row address /256 column address
•
Refresh cycles
⎯
4096 refresh cycles/64ms
•
2 variations of refresh
⎯
Auto refresh
⎯
Self refresh
•
FBGA package with lead free solder (Sn-Ag-Cu)
C
VSSQ DQ27 DQ25
D
VSSQ DQ29 DQ30
E
VDDQ DQ31
NC
A3
A6
A12
A9
NC
F
VSS DQM3
Document No. E0462E30 (Ver. 3.0)
Date Published July 2004 (K) Japan
URL: http://www.elpida.com
L
G
A4
A5
A8
CKE
NC
H
A7
J
CLK
K
DQM1
/WE DQM0
DQ7 VSSQ
DQ5 VDDQ
DQ3 VDDQ
od
Pr
L
VDDQ DQ8
VSS
M
N
P
VSSQ DQ10 DQ9
VSSQ DQ12 DQ14
DQ11 VDDQ VSSQ
DQ13 DQ15 VSS
VDDQ VSSQ DQ4
VDD
DQ0
DQ2
R
(Top view)
Address inputs
Bank select address
Data-input/output
Chip select
Row address strobe
Column address strobe
Write enable
DQ mask enable
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
A0 to A12
BA0, BA1
DQ0 to DQ31
/CS
/RAS
/CAS
/WE
DQM0 to DQM3
CKE
CLK
VDD
VSS
VDDQ
VSSQ
NC
This product became EOL in March, 2007.
©Elpida
Memory, Inc. 2004
t
uc
ELPIDA [ ELPIDA MEMORY ]
