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EDS5104ABTA-7A 参数 Datasheet PDF下载

EDS5104ABTA-7A图片预览
型号: EDS5104ABTA-7A
PDF下载: 下载PDF文件 查看货源
内容描述: 512M位的SDRAM [512M bits SDRAM]
分类和应用: 动态存储器
文件页数/大小: 52 页 / 558 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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PRELIMINARY DATA SHEET
512M bits SDRAM
EDS5104ABTA (128M words
×
4 bits)
EDS5108ABTA (64M words
×
8 bits)
EDS5116ABTA (32M words
×
16 bits)
Description
The EDS5104AB is a 512M bits SDRAM organized as
33,554,432 words
×
4 bits
×
4 banks. The EDS5108AB
is a 512M bits SDRAM organized as 16,777,216 words
×
8 bits
×
4 banks. The EDS5116AB is a 512M bits
SDRAM organized as 8,388,608 words
×
16 bits
×
4
banks. All inputs and outputs are referred to the rising
edge of the clock input. It is packaged in standard 54-
pin plastic TSOP (II).
Pin Configurations
/xxx indicates active low signal.
54-pin TSOP
VDD VDD
NC DQ0
NC
NC
DQ0 DQ1
NC
NC
NC DQ2
NC
NC
DQ1 DQ3
NC
VDD
NC
/WE
/CAS
/RAS
/CS
BA0
BA1
A10
A0
A1
A2
A3
VDD
VDD
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS VSS VSS
DQ15 DQ7 NC
VSSQ VSSQ VSSQ
VDDQ VDDQ VDDQ
DQ14 NC NC
DQ13 DQ6 DQ3
VDDQ VDDQ VDDQ
VSSQ VSSQ VSSQ
Features
3.3V power supply
Clock frequency: 166MHz/133MHz (max.)
LVTTL interface
Single pulsed /RAS
4 banks can operate simultaneously and
independently
Burst read/write operation and burst read/single write
operation capability
Programmable burst length (BL): 1, 2, 4, 8, full page
2 variations of burst sequence
Sequential (BL = 1, 2, 4, 8, full page)
Interleave (BL = 1, 2, 4, 8)
Programmable /CAS latency (CL): 2, 3
Byte control by DQM
: DQM (EDS5104AB, EDS5108AB)
: UDQM, LDQM (EDS5116AB)
Refresh cycles: 8192 refresh cycles/64ms
2 variations of refresh
Auto refresh
Self refresh
DQ12 NC NC
DQ11 DQ5 NC
VSSQ VSSQ VSSQ
VDDQ VDDQ VDDQ
DQ10 NC NC
DQ9 DQ4 DQ2
VDDQ VDDQ VDDQ
VSSQ VSSQ VSSQ
NC DQ7
VDD VDD
NC LDQM
/WE /WE
/CAS /CAS
/RAS /RAS
/CS
/CS
BA0 BA0
BA1 BA1
A10 A10
A0
A0
A1
A1
A2
A2
A3
A3
VDD VDD
DQ8 NC
VSS VSS
NC
NC
UDQM DQM
CLK CLK
CKE CKE
A12 A12
A11 A11
A9
A9
A8
A8
A7
A7
A6
A6
A5
A5
A4
A4
VSS VSS
NC
VSS
NC
DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
VSS
X 16
X8
X4
(Top view)
A0 to A12,
BA0, BA1
Address input
Bank select address
DQ0 to DQ15
Data-input/output
/CS
Chip select
/RAS
Row address strobe
Column address strobe
/CAS
Write enable
/WE
DQM
CKE
CLK
VDD
VSS
Input/output mask
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
VDDQ
Power for DQ circuit
VSSQ
Ground for DQ circuit
NC
No connection
Document No. E0250E10 (Ver. 1.0)
Date Published March 2002 (K) Japan
URL: http://www.elpida.com
Elpida
Memory, Inc. 2002