欢迎访问ic37.com |
会员登录 免费注册
发布采购

EDS6432AFTA-75TI-E 参数 Datasheet PDF下载

EDS6432AFTA-75TI-E图片预览
型号: EDS6432AFTA-75TI-E
PDF下载: 下载PDF文件 查看货源
内容描述: 64M位SDRAM WTR (宽温度范围) [64M bits SDRAM WTR (Wide Temperature Range)]
分类和应用: 动态存储器
文件页数/大小: 49 页 / 690 K
品牌: ELPIDA [ ELPIDA MEMORY ]
 浏览型号EDS6432AFTA-75TI-E的Datasheet PDF文件第2页浏览型号EDS6432AFTA-75TI-E的Datasheet PDF文件第3页浏览型号EDS6432AFTA-75TI-E的Datasheet PDF文件第4页浏览型号EDS6432AFTA-75TI-E的Datasheet PDF文件第5页浏览型号EDS6432AFTA-75TI-E的Datasheet PDF文件第6页浏览型号EDS6432AFTA-75TI-E的Datasheet PDF文件第7页浏览型号EDS6432AFTA-75TI-E的Datasheet PDF文件第8页浏览型号EDS6432AFTA-75TI-E的Datasheet PDF文件第9页  
PRELIMINARY DATA SHEET
64M bits SDRAM
WTR (Wide Temperature Range)
EDS6432AFTA-TI (2M words
×
32 bits)
Description
The EDS6432AFTA is a 64M bits SDRAM organized
as 524,288 words
×
32 bits
×
4 banks. All inputs and
outputs are synchronized with the positive edge of the
clock.
It is packaged in 86-pin plastic TSOP (II).
Pin Configurations
/xxx indicate active low signal.
86-pin Plastic TSOP(II)
Features
3.3V power supply
Clock frequency: 133MHz (max.)
Single pulsed /RAS
×32
organization
4 banks can operate simultaneously and
independently
Burst read/write operation and burst read/single
write operation capability
2 variations of burst sequence
Sequential (BL = 1, 2, 4, 8, full page)
Interleave (BL = 1, 2, 4, 8)
Programmable /CAS latency (CL): 2, 3
Byte control by DQM
Refresh cycles: 4096 refresh cycles/64ms
2 variations of refresh
Auto refresh
Self refresh
TSOP (II) package with lead free solder (Sn-Bi)
Wide temperature range
Ambient temperature range: –40 to +85°C
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDD
DQM0
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10(AP)
A0
A1
A2
DQM2
VDD
NC
DQ16
VSSQ
DQ17
DQ18
VDDQ
DQ19
DQ20
VSSQ
DQ21
DQ22
VDDQ
DQ23
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSS
DQM1
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
VSS
NC
DQ31
VDDQ
DQ30
DQ29
VSSQ
DQ28
DQ27
VDDQ
DQ26
DQ25
VSSQ
DQ24
VSS
(Top view)
A0 to A10
BA0, BA1
DQ0 to DQ31
/CS
/RAS
/CAS
/WE
CKE
CLK
VDD
VSS
VDDQ
VSSQ
Address input
Bank select address
Data-input/output
Chip select
Row address strobe
Column address strobe
Write enable
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground
for DQ circuit
DQM0 to DQM3
Input output mask
NC
No connection
Document No. E0630E10 (Ver. 1.0)
Date Published December 2004 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida
Memory, Inc. 2004