HM5212165FTD-75/A60/B60
HM5212805FTD-75/A60/B60
Description
The HM5212165F is a 128-Mbit SDRAM organized as 2097152-word
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16-bit
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4-bank. The HM5212805F is
a 128-Mbit S DRA M orga nized as 4194304-w ord
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8-bit
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4-ba nk. All inputs and outputs ar e re fe rre d to the
rising edge of the clock input. It is packaged in standard 54-pin plastic TSOP II.
Features
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3.3 V power supply
Clock frequency: 133 MHz/100 MHz (max)
LVTTL interface
Single pulsed
RAS
4 banks can operate simultaneously and independently
Burst read/write operation and burst read/single write operation capability
Programmable burst length: 1/2/4/8/full page
2 variations of burst sequence
Sequential (BL = 1/2/4/8/full page)
Interleave (BL = 1/2/4/8)
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Programmable
CAS
latency: 2/3
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Byte control by DQM : DQM (HM5212805F)
: DQMU/DQML (HM5212165F)
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Refresh cycles: 4096 refresh cycles/64 ms
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
L
EO
128M LVTTL interface SDRAM
133 MHz/100 MHz
2-Mword
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16-bit
×
4-bank/4-Mword
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8-bit
×
4-bank
PC/133, PC/100 SDRAM
E0179H10 (Ver. 1.0)
Jul. 16, 2001
This product became EOL in June, 2005.
Pr
od
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ELPIDA [ ELPIDA MEMORY ]
