HM5259165B/HM5259805B/HM5259405B-75/A6
Block Diagram
(HM5259165B)
A0 to A12, BA0, BA1
Upper pellet
A0 to A9
Column address
counter
Column address
buffer
A0 to A12, BA0, BA1
Row address
buffer
Refresh
counter
Row decoder
Sense amplifier & I/O bus
Sense amplifier & I/O bus
Row decoder
Sense amplifier & I/O bus
Row decoder
Sense amplifier & I/O bus
Row decoder
Memory array
Column decoder
Bank0
8192 row
×
1024 column
×
8 bit
Memory array
Column decoder
Bank1
8192 row
×
1024 column
×
8 bit
Memory array
Column decoder
Bank2
8192 row
×
1024 column
×
8 bit
Memory array
Bank3
8192 row
×
1024 column
×
8 bit
Column decoder
Input buffer
Output buffer
CLK
CKE
Control logic &
timing generator
CS
RAS
CAS
WE
DQMU
/DQML
DQ8 to DQ15
DQ0 to DQ7
Input buffer
Output buffer
Sense amplifier & I/O bus
Sense amplifier & I/O bus
Sense amplifier & I/O bus
Sense amplifier & I/O bus
Memory array
Column decoder
Bank0
8192 row
×
1024 column
×
8 bit
Memory array
Column decoder
Bank1
8192 row
×
1024 column
×
8 bit
Memory array
Column decoder
Bank2
8192 row
×
1024 column
×
8 bit
Memory array
Bank3
8192 row
×
1024 column
×
8 bit
Column decoder
Row decoder
Row decoder
Row decoder
Row decoder
Column address
counter
Column address
buffer
Row address
buffer
Refresh
counter
Lower pellet
Data Sheet E0118H10
6