EM39LV800
8M Bits (512Kx16) Flash Memory
SPECIFICATION
Sector/Block Erase
The EM39LV800 offers both Sector-Erase and Block-Erase modes. The Sector- (or Block-)
Erase operation allows the system to erase the device on a sector-by-sector (or
block-by-block) basis. The sector architecture is based on uniform sector size of 2 KWord.
The Block architecture is based on uniform block size of 32 KWord. The Sector-Erase
operation is initiated by executing a six-byte command sequence with Sector-Erase command
(30H) and sector address (SA) in the last bus cycle. The Block-Erase operation is initiated by
executing a six-byte command sequence with Block-Erase command (50H) and block
address (BA) in the last bus cycle. The sector or block address is latched on the falling edge
of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the
sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The
End-of-Erase operation can be determined by using either Data# Polling or Toggle Bit
method. See Figures 7 and 8 for timing waveforms. Any commands issued during the
Sector or Block Erase operation are ignored.
Data# Polling (DQ7)
When the EM39LV800 is in the internal Program operation, any attempt to read DQ7 will
produce the complement of the true data. Once the Program operation is completed, DQ7
will produce the true data. Note that even though DQ7 may have valid data immediately
following the completion of an internal Program operation, the remaining data outputs may still
be invalid (valid data on the entire data bus will appear in subsequent successive Read cycles
after an interval of 1 µs). During internal Erase operation, any attempt to read DQ7 will
produce a ‘0’. Once the internal Erase operation is completed, DQ7 will produce a ‘1’. The
Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation.
For Sector-Erase, Block-Erase, or Chip-Erase, the Data# Polling is valid after the rising edge
of sixth WE# (or CE#) pulse. See Figure 4 for Data# Polling timing diagram and Figure 14 for
a flowchart.
Toggle Bit (DQ6)
During the internal Program or Erase operation, any consecutive attempts to read DQ6 will
produce alternating 1s and 0s, i.e., toggling between 1 and 0. When the internal Program or
Erase operation is completed, the DQ6 bit will stop toggling. The device is then ready for the
next operation. The Toggle Bit is valid after the rising edge of fourth WE# (or CE#) pulse for
Program operation. For Sector-Erase, Block-Erase or Chip-Erase, the Toggle Bit is valid
after the rising edge of sixth WE# (or CE#) pulse. See Figure 5 for Toggle Bit timing diagram
and Figure 14 for a flowchart.
Data Protection
The EM39LV800 provides both hardware and software features to protect the data from
inadvertent write.
This specification is subject to change without further notice. (04.09.2004 V1.0)
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EMC [ ELAN MICROELECTRONICS CORP ]
