EM78911
* The relation between Bit0 to Bit3 is shown in Fig.6.
SLEEP MODE
Begin
set /FSKPWR='0'
/RINGTIME ='0'
or external keys
pressed
sleep mode
/RINGTIME ='0'
or external keys
pressed
No
/RD and /CD ='1'
Yes
/RD and /CD ='1' and
nothing to do for 30
sec , /FSKPWR='0'
WAKE UP MODE
8-bit wake up andꢀ
set /FSKPWR='1'
accept data from
FSK decoder
wake up
mode
/FSKPWR='1'
FSK decoder
begin its work
DATA transfer
to Micro
/RD and /CD ='1'
data end and 30
sec nothing to do.
No
Yes
Flow Diagram between 8-bit
and FSK decoder
STATE Diagram between 8-bit
and FSK decoder
Fig6. The relation between Bit0 to Bit3.
* Bit4(Read Only)(Low battery signal) 0/1 = Battery voltage is low/Normal .
If the VDD voltage is under low power range (controlled by IOCA bit0) then sends a '0' signal to
/LOW_BAT bit or a '1' signal to this Bit.
* Bit5(read/Write)(Low battery detect enable)
0/1 = low battery detect DISABLE/ENABLE.
The relation between /LPD,/POVD and /LOW_BAT can see Fig7.
Vdd
/POVD
/LPD
s2
1 on
0 off
to Low bat
1 on
+
-
To reset
1 on
Vref
s2
1 on
0 off
/LPD
Fig7. The relation between /LPD,/POVD
* Bit6(read/write)(PLL enable signal)
0/1=DISABLE/ENABLE
The relation between 32.768K and 3.579M can see Fig8.
P L L
3 . 5 7 9 M H z
1
S u b - c l o c k
3 2 . 7 6 8 K H z
R A b i t6
s w i t c h
0
T o s y s t e m c l o c k
Fig8. The relation between 32.768K and 3.579K .
8
ELAN [ ELAN MICROELECTRONICS CORP ]
