EM78P156E
Address
Name
Reset Type
Bit Name
Power-on
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
/PD7 /PD6 /PD5 /PD4
X
U
U
U
/PD2 /PD1 /PD0
0x0B
IOCB
1
1
P
1
1
P
1
1
P
1
1
P
1
1
P
1
1
P
1
1
P
/RESET and WDT
Wake-up from Pin Changed
Bit Name
OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0
0x0C
0x0D
0x0E
0x0F
IOCC
IOCD
Power-on
0
0
P
0
0
P
0
0
P
0
0
P
0
0
P
0
0
P
0
0
P
0
0
P
/RESET and WDT
Wake-up from Pin Changed
Bit Name
/PH7 /PH6 /PH5 /PH4 /PH3 /PH2 /PH1 /PH0
Power-on
1
1
P
1
1
P
1
1
P
1
1
P
ROC
0
0
1
1
P
1
1
P
X
U
U
U
1
1
P
X
U
U
U
1
1
P
X
U
U
U
/RESET and WDT
Wake-up from Pin Changed
Bit Name
WDTC EIS
X
U
U
U
X
U
U
U
-
X
U
U
U
X
U
U
U
-
IOCE
Power-on
1
1
1
X
U
U
U
-
0
0
/RESET and WDT
Wake-up from Pin Changed
Bit Name
P
X
U
U
U
-
P
X
U
U
U
-
EXIE ICIE TCIE
IOCF
Power-on
0
0
P
-
0
0
P
-
0
0
P
-
/RESET and WDT
Wake-up from Pin Changed
Bit Name
0x10
~ 0x3F
R10~R3F
Power-on
/RESET and WDT
Wake-up from Pin Changed
U
P
P
U
P
P
U
P
P
U
P
P
U
P
P
U
P
P
U
P
P
U
P
P
** To jump address 0x08, or to execute the instruction which is next to the “SLEP” instruction.
X: not used.
U: unknown or don’t care.
P: previous value before reset.
t: check Table 4
2. The status of T and P of STATUS register
A RESET condition can be caused by the following events:
1. a power-on condition,
2. a high-low-high pulse on /RESET pin, and
3. Watchdog Timer time-out.
The values of T and P, listed in Table 4 can be used to check how the processor wakes up. Table 5 shows the events which
may affect the status of T and P .
Table 4 The values of T and P after RESET
Reset Type
Power-on
T
1
P
1
/RESET during operating mode
/RESET wake-up during SLEEP mode
WDT during operating mode
*P
1
0
*P
0
P
WDT wake-up during SLEEP mode
Wake-up on pin changed during SLEEP mode
0
1
0
0
*P: Previous status before reset
* This specification is subject to be changed without notice. 8.11.1999
B3-15
ELAN [ ELAN MICROELECTRONICS CORP ]
