EM78P813
8-bit OTP Micro-controller
VI. Pin Descriptions
I. POWER pin
Pin
VDD
AVDD
LVDD
GND
AVSS
LVSS
II. CLOCK pin
Pin
XIN
XOUT
PLLC
I/O
POWER
POWER
POWER
POWER
POWER
POWER
I/O
I
O
I
Description
Digital Power
Analog Power
Charge pump used power
Digital Ground
Analog Ground
Charge pump used power
Description
Input pin for 32.768 kHz oscillator
Output pin for 32.768 kHz oscillator
Phase loop lock capacitor, connect a capacitor 0.01u to 0.047u
with GND
III.1. Embedded LCD pin
Pin
COM0..COM15
COM16..COM23
COM24..COM31
SEG0..SEG65
SEG66..SEG73
SEG74..SEG81
SEG82..SEG89
SEG90..SEG97
C1,C2
Vout
VREF
VC1..VC5
Description
Common driver pins of LCD drivers
COM16..COM23 are shared with SEG111..SEG106
COM24..COM31 are shared with SEG105..SEG98
Segment driver pins of LCD drivers
Segment driver pins of LCD drivers share with PORT8
Segment driver pins of LCD drivers share with PORT9
Segment driver pins of LCD drivers share with PORTB
Segment driver pins of LCD drivers share with PORTC
Charge Pump capacitor. C1 connect 1uF Cap To C2.
Charge pump output voltage ,connect 1uF Cap to GND
2.7V, need to be connected 0.1uF capacitor to GND
Reference voltage input. Each one connect a capacitor (0.1u)
with GND.
III.2. External LCD device control pin
Pin
I/O
Description
LCDD0..LCDD7
I/O
External LCD driver data bus. Shared with PORTB0..PORTB7.
/WR
O
Write enable output (active low signal). Shared with PORTC2.
/RD
O
Read enable output (active low signal). Shared with PORTC3.
A0
O
Used as register selection. When A0 equal to 1, data bus transmit
LCD DATA. When A0 equal to 0,data bus transmit LCD
Address. The pin shared with PORTC4.
/CS1../CS2
O
Chip Selection signal output. Shared with PORTC1..PORTC0
IV. FSK,CW
Pin
I/O
Description
TIP
I
Should be connected with TIP side of twisted pair lines for FSK.
RING
I
Should be connected with RING side of twisted pair lines for
FSK.
CWGS
O
Gain adjustment of single-ended input OP Amp
CWIN
I
Single-ended input OP Amp for call waiting decoder
EGIN1,EGIN2
I
DED input
V. DTMF receiver
Pin
I/O
Description
EST
O
Early steering output. Presents a logic high immediately when
__________________________________________________________________________________________________________________________________________________________________
I/O
O
O
O
O
O
O
O
O
-
-
-
I
* This specification is subject to change without notice.
8
2004/8/19 (V1.6)