EM92600/1A
DUAL PLL FOR 46/49 MHZ CORDLESS PHONE
Symbol
D0
D1
D2
D3
Di
CLK
NC
EN
TIF
LD
PDT
V
SS
PDR
RIF
V
DD
XTAL1
I/O
I
I
I
I
I
I
-
I
I
O
O
-
O
I
-
I
Function
The channel selected pin. LSB.(intenal pull down)
The channel selected pin. (internal pull down)
The channel selected pin. (internal pull down)
The channel selected pin. MSB.(internal pull down)
The serial input data pin.
Clock input. Each low to high transition of the clock shifts one bit of data into
the on-chip shift register.
Not connect.
The enable pin controls the data transfer from the shift register to the 4-bit latch.
A low to high transition latches the data.
Input to programmable divider of Tx. AC coupling with VCO. Min input voltage
is 200mVpp.
Unlock detector output. V
DD
level: unlock.
Phase detector output for Tx. PDT detects the phase error from Tx PLL and its
output is connected to external low pass filter.
Ground.
Phase detector output for Rx. PDR detects the phase error from Rx PLL and its
output is connected to external low pass filter.
Input of programmable divider for Rx.AC coupling with VCO. Min input voltage
is 200mVpp.
Power supply.
To connect crystal ( 10.240MHz ) and capacitor.
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DD
V
IN
I
IN
,I
OUT
I
DD
,I
SS
T
A
T
STG
Rating
DC supply voltage
Input voltage
DC current drain per pin
DC current drain V
DD
or V
SS
pins
Operating temperature range
Storage temperature range
Value
-0.5 to +6
-0.5 to V
DD
+0.5
10.0
30.0
-30 to +75
-65 to +150
Unit
V
V
mA
mA
°C
°C
* This specification are subject to be changed without notice.
4.23.1995
3
EMC [ ELAN MICROELECTRONICS CORP ]
