EM620FU8B
TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 CONTROLLED)
Low Power, 256Kx8 SRAM
t
WC
Address
t
CW1,2
(2)
CS1
t
AS
(3)
CS2
t
AW
t
WP
(1)
WE
t
DW
Data in
High-Z
Data Valid
t
WR
(4)
t
DH
Data out
High-Z
NOTES
(WRITE CYCLE)
1. A write occurs during the overlap(t
WP
) of low CS1, a high CS2 and low WE. A write begins at the latest
transition among CS1 goes low, CS2 goes high and WE goes low. A write ends at the earliest transition
among CS1 goes high, CS2 goes low and WE goes high. The t
WP
is measured from the beginning of write
to the end of write.
2. t
CW
is measured from the CS1 going low or CS2 going high to end of write.
3. t
AS
is measured from the address valid to the beginning of write.
4. t
WR
is measured from the end or write to the address change. t
WR
applied in case a write ends as CS1
or WE going high or CS2 going low.
8
EMLSI [ Emerging Memory & Logic Solutions Inc ]
