EM620FU8BT Series
Low Power, 256Kx8 SRAM
V
TM3)
R
12)
AC OPERATING CONDITIONS
Test Conditions (Test
Load and Test Input/Output Reference)
Input Pulse Level : 0.4V to 2.2V
Input Rise and Fall Time : 5ns
Input and Output reference Voltage : 1.5V
Output Load (See right) : CL
1)
= 100pF + 1 TTL (70ns)
CL
1)
= 30pF + 1 TTL (45ns/55ns)
1. Including scope and Jig capacitance
2. R
1
=3070 ohm
,
R
2
=3150 ohm
3. V
TM
=2.8V
4. CL = 5pF + 1 TTL (measurement with t
LZ1,2
, t
HZ1,2
, t
OLZ
, t
OHZ
, t
WHZ
)
CL
1)
R
22)
READ CYCLE
(V
cc
= 2.7V to 3.3V, Gnd = 0V, T
A
= -40
o
C to +85
o
C)
Parameter
Read cycle time
Address access time
Chip select to output
Output enable to valid output
Chip select to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
Output disable to high-Z output
Output hold from address change
Symbol
t
RC
t
AA
t
CO1,
t
CO2
t
OE
t
LZ1,
t
LZ2
t
OLZ
t
HZ1,
t
HZ2
t
OHZ
t
OH
45ns
Min
45
-
-
-
10
5
0
0
10
Max
-
45
45
25
-
-
20
15
-
Min
55
-
-
-
10
5
0
0
10
55ns
Max
-
55
55
25
-
-
20
20
-
Min
70
-
-
-
10
5
0
0
10
70ns
Max
-
70
70
35
-
-
25
25
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
WRITE CYCLE
(V
cc
= 2.7V to 3.3V, Gnd = 0V, T
A
= -40
o
C to +85
o
C)
Parameter
Write cycle time
Chip select to end of write
Address setup time
Address valid to end of write
Write pulse width
Write recovery time
Write to ouput high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
Symbol
t
WC
t
CW1,
t
CW2
t
AS
t
AW
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
45ns
Min
45
45
0
45
35
0
0
25
0
5
-
-
Max
-
-
-
-
-
-
15
55
45
0
45
40
0
0
25
0
5
55ns
Min
Max
-
-
-
-
-
-
20
Min
70
60
0
60
50
0
0
30
-
-
0
5
70ns
Max
-
-
-
-
-
-
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
-
-
ns
ns
5
EMLSI [ Emerging Memory & Logic Solutions Inc ]
