EM641FT8
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Transition Controlled)
Low Power, 512Kx8 SRAM
t
RC
Address
t
AA
t
OH
Data Out
Previous Data Valid
Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (OE Controlled)
t
RC
Address
t
AA
CS
t
OE
OE
t
OLZ
Data Out
High-Z
t
LZ
Data Valid
t
CO
t
OH
t
HZ
t
OHZ
High-Z
NOTES
(READ CYCLE)
1. t
HZ
and t
OHZ
are defined as the outputs achieve the open circuit conditions and are not referenced to output voltage levels.
2. At any given temperature and voltage condition, t
HZ
(Max.) is less than t
LZ
(Min.) both for a given device and from device to device
interconnection.
6